[HLSL] `ElementWise_BitCount_256.*` DML shaders directly cause 49 operator test failures on NVIDIA and Intel

[Icohedron]

49 DML operator test failures consistent across devices with NVIDIA and Intel GPUs are confirmed to be caused by the following shaders:

ElementWise_BitCount_256_4_uint16_native_uint32_native
ElementWise_BitCount_256_8_uint16_native_uint32_native

Failing tests: (Note that NVIDIA 40 series and Intel fail the following tests. AMD and NVIDIA 50 series passes these tests.)

OperatorTests::ElementWise_BitCount#121
OperatorTests::ElementWise_BitCount#128
OperatorTests::ElementWise_BitCount#136
OperatorTests::ElementWise_BitCount#144
OperatorTests::ElementWise_BitCount#149
OperatorTests::ElementWise_BitCount#15
OperatorTests::ElementWise_BitCount#167
OperatorTests::ElementWise_BitCount#190
OperatorTests::ElementWise_BitCount#198
OperatorTests::ElementWise_BitCount#199
OperatorTests::ElementWise_BitCount#210
OperatorTests::ElementWise_BitCount#218
OperatorTests::ElementWise_BitCount#231
OperatorTests::ElementWise_BitCount#233
OperatorTests::ElementWise_BitCount#242
OperatorTests::ElementWise_BitCount#254
OperatorTests::ElementWise_BitCount#256
OperatorTests::ElementWise_BitCount#258
OperatorTests::ElementWise_BitCount#259
OperatorTests::ElementWise_BitCount#269
OperatorTests::ElementWise_BitCount#27
OperatorTests::ElementWise_BitCount#275
OperatorTests::ElementWise_BitCount#302
OperatorTests::ElementWise_BitCount#340
OperatorTests::ElementWise_BitCount#350
OperatorTests::ElementWise_BitCount#361
OperatorTests::ElementWise_BitCount#383
OperatorTests::ElementWise_BitCount#392
OperatorTests::ElementWise_BitCount#400
OperatorTests::ElementWise_BitCount#403
OperatorTests::ElementWise_BitCount#409
OperatorTests::ElementWise_BitCount#414
OperatorTests::ElementWise_BitCount#417
OperatorTests::ElementWise_BitCount#42
OperatorTests::ElementWise_BitCount#451
OperatorTests::ElementWise_BitCount#467
OperatorTests::ElementWise_BitCount#481
OperatorTests::ElementWise_BitCount#487
OperatorTests::ElementWise_BitCount#518
OperatorTests::ElementWise_BitCount#519
OperatorTests::ElementWise_BitCount#52
OperatorTests::ElementWise_BitCount#535
OperatorTests::ElementWise_BitCount#54
OperatorTests::ElementWise_BitCount#544
OperatorTests::ElementWise_BitCount#55
OperatorTests::ElementWise_BitCount#61
OperatorTests::ElementWise_BitCount#63
OperatorTests::ElementWise_BitCount#66
OperatorTests::ElementWise_BitCount#89
OperatorTests::ElementWise_BitCount#9

Sample Reproduction

> .\TE.exe DirectML.Test.OperatorTests.dll /name:"OperatorTests::ElementWise_BitCount#121" /p:DisableMetacommands=1 /logOutput:low
Test Authoring and Execution Framework v10.72 for x64

StartGroup: OperatorTests::ElementWise_BitCount#121
Error: Output Tensor #0:
Error: Tensor Sizes: 1
Error: Tensor Data Type: uint32
Error: Index: 0000 @00000000 [0].  Ref: 11 (0x0000000B)  DML: 4294901771 (0xFFFF000B)  Abs: 4294901760.000000.  Rel: 100.000000%.  Ulp: 4294901760
Error: 1 / 1 (100.000000%) of elements were found to be above tolerance.
Error: Max ULP delta: 4294901760.  Allowed tolerance: 0 ULPs (uint32).
Error: Verify: Fail [File: C:\__w\1\s\DirectML\SharedToolingLib\External\Test\TaefHelper\TaefHelper.cpp, Function: TaefHelper::Fail, Line: 133]
EndGroup: OperatorTests::ElementWise_BitCount#121 [Failed]

Summary of Non-passing Tests:
    OperatorTests::ElementWise_BitCount#121 [Failed]

Summary: Total=1, Passed=0, Failed=1, Blocked=0, Not Run=0, Skipped=0

[Icohedron]

These are driver bugs for the NVIDIA 4070 and the Intel Arc A750.
For Intel, the issue appears to be the same as reported under internal bug 59923946 where the storing of the i32 is only storing the first 16 bits rather than the full 32 bits.

The issue for the NVIDIA 4070 appears to be due to the 16-bit variant of the countbits DXIL op.
This issue is filed under internal bug 60079876.

Clang emits

%6 = call i32 @dx.op.unaryBits.i16(i32 31, i16 %5) ; where %5 = 57313

While DXC emits

%17 = zext i16 %16 to i32 ; where %16 = 57313
%18 = call i32 @dx.op.unaryBits.i32(i32 31, i32 %17)

On the NVIDIA 4070, the result of %6 is 27 while the result of %18 is 11.
This implies that @dx.op.unaryBits.i16(i32 31, i16 <arg>) is sign-extending its input to 32 bits before counting the bits.