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Missing optimization (fold of ashr and sext) #3010

@llvmbot

Description

@llvmbot
Bugzilla Link 2638
Resolution FIXED
Resolved on Nov 07, 2018 00:21
Version unspecified
OS All
Attachments Input .c file
Reporter LLVM Bugzilla Contributor
CC @lattner

Extended Description

LLVM misses some optimization of the attached test case:

ddunbar@ddunbar2:CodeGen$ llvm-gcc -c --emit-llvm -o - ~/rt/gaz.c | opt -std-compile-opts | llvm-dis
; ModuleID = ''
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9"

define i32 @​foo(i32 %i) nounwind {
entry:
%tmp12 = trunc i32 %i to i8 ; [#uses=1]
%tmp16 = shl i8 %tmp12, 6 ; [#uses=1]
%sextr23 = ashr i8 %tmp16, 6 ; [#uses=1]
%sextr2324 = sext i8 %sextr23 to i32 ; [#uses=1]
ret i32 %sextr2324
}

For reference, here is the bytecode that comes from the IR generated by clang, after optimization:
-- clang --
; ModuleID = ''
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i686-apple-darwin9.4.0"

define i32 @​foo(i32 %i) nounwind {
entry:
%tmp9 = shl i32 %i, 30 ; [#uses=1]
%tmp10 = ashr i32 %tmp9, 30 ; [#uses=1]
ret i32 %tmp10
}

The difference comes from the way the bitfield load is generated....

No clue if this is worthwhile.

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