[Loop Vectorizer] Loop Vectorized with Gather Instead of Load Due to SUB => XOR Transformation

[mmarjieh]

Starting from Clang 18, I get a masked_gather instead of regular load in vectorizer.

Reproducer:
Top of Trunk Clang:
https://godbolt.org/z/aj91K1eaf
See LoopVectorize debug prints:

LAA: Bad stride - Not an AddRecExpr pointer %arrayidx = getelementptr inbounds i32, ptr %a1, i64 %idxprom, !dbg !26 SCEV: ((4 * %idxprom) + %a1)

Clang 17:
https://godbolt.org/z/Y9W56Wds5

I believe that the issue is happening due to instcombine transforming SUB -> XOR. Does it load unscevable pattern?

[topperc]

Looks like InstCombine used computeKnownBits to prove that the upper bits were 0 using the dominating condition from the < 256 check created by the loop

I tried to teach SCEV to reverse the transform, but I think loop rotation prevented the fact from being provable by computeKnownBits later.

CC: @nikic

[nikic]

Dominating conditions are only available in InstCombine, so if they are used to infer KnownBits, you usually cannot undo them easily.

I think an acceptable fix here would be to skip use of dominating conditions in the sub -> xor canonicalization. (For purely canonicalizing transforms, if there is no flag to undo, it's probably best not to use dominating conditions.)

[topperc]

Dominating conditions are only available in InstCombine, so if they are used to infer KnownBits, you usually cannot undo them easily.

I think an acceptable fix here would be to skip use of dominating conditions in the sub -> xor canonicalization. (For purely canonicalizing transforms, if there is no flag to undo, it's probably best not to use dominating conditions.)

Is there an existing way to disable it?

[nikic]

@topperc You'd want to add a getWithoutDomCondCache() method to SimplifyQuery for this, which nulls out DC.