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[RISCV] Add riscv_vlm/vsm to RISCVTargetLowering::getTgtMemIntrinsic. #148265

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Merged
merged 1 commit into from
Jul 11, 2025
Merged

[RISCV] Add riscv_vlm/vsm to RISCVTargetLowering::getTgtMemIntrinsic. #148265

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6 changes: 2 additions & 4 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2268,8 +2268,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
MachineSDNode *Load =
CurDAG->getMachineNode(P->Pseudo, DL, Node->getVTList(), Operands);

if (auto *MemOp = dyn_cast<MemSDNode>(Node))
CurDAG->setNodeMemRefs(Load, {MemOp->getMemOperand()});
CurDAG->setNodeMemRefs(Load, {cast<MemSDNode>(Node)->getMemOperand()});

ReplaceNode(Node, Load);
return;
Expand Down Expand Up @@ -2487,8 +2486,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
IsMasked, IsStrided, Log2SEW, static_cast<unsigned>(LMUL));
MachineSDNode *Store =
CurDAG->getMachineNode(P->Pseudo, DL, Node->getVTList(), Operands);
if (auto *MemOp = dyn_cast<MemSDNode>(Node))
CurDAG->setNodeMemRefs(Store, {MemOp->getMemOperand()});
CurDAG->setNodeMemRefs(Store, {cast<MemSDNode>(Node)->getMemOperand()});

ReplaceNode(Node, Store);
return;
Expand Down
8 changes: 7 additions & 1 deletion llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1772,7 +1772,7 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
->getZExtValue());
Info.align = DL.getABITypeAlign(MemTy);
} else {
Info.align = Align(DL.getTypeSizeInBits(MemTy->getScalarType()) / 8);
Info.align = Align(DL.getTypeStoreSize(MemTy->getScalarType()));
}
Info.size = MemoryLocation::UnknownSize;
Info.flags |=
Expand Down Expand Up @@ -1824,6 +1824,11 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
return SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 3,
/*IsStore*/ true,
/*IsUnitStrided*/ false, /*UsePtrVal*/ true);
case Intrinsic::riscv_vlm:
return SetRVVLoadStoreInfo(/*PtrOp*/ 0,
/*IsStore*/ false,
/*IsUnitStrided*/ true,
/*UsePtrVal*/ true);
case Intrinsic::riscv_vle:
case Intrinsic::riscv_vle_mask:
case Intrinsic::riscv_vleff:
Expand All @@ -1832,6 +1837,7 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
/*IsStore*/ false,
/*IsUnitStrided*/ true,
/*UsePtrVal*/ true);
case Intrinsic::riscv_vsm:
case Intrinsic::riscv_vse:
case Intrinsic::riscv_vse_mask:
return SetRVVLoadStoreInfo(/*PtrOp*/ 1,
Expand Down
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