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[DAG] getNode - fold (sext (trunc x)) -> x iff the upper bits are already signbits #151945

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Merged
RKSimon merged 3 commits into from
Aug 6, 2025
+30 −15
Merged

[DAG] getNode - fold (sext (trunc x)) -> x iff the upper bits are already signbits #151945

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353d76c
[DAG] getNode - fold (sext (trunc x)) -> x iff the upper bits are all…
RKSimon Aug 4, 2025
519ac4c
Merge branch 'main' into dag-remove-unnecessary-sextinreg
RKSimon Aug 6, 2025
1b03d89
Merge branch 'main' into dag-remove-unnecessary-sextinreg
RKSimon Aug 6, 2025
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14 changes: 14 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6422,6 +6422,20 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
if (N1.isUndef())
// sext(undef) = 0, because the top bits will all be the same.
return getConstant(0, DL, VT);

// Skip unnecessary sext_inreg pattern:
// (sext (trunc x)) -> x iff the upper bits are all signbits.
if (OpOpcode == ISD::TRUNCATE) {
SDValue OpOp = N1.getOperand(0);
if (OpOp.getValueType() == VT) {
unsigned NumSignExtBits =
VT.getScalarSizeInBits() - N1.getScalarValueSizeInBits();
if (ComputeNumSignBits(OpOp) > NumSignExtBits) {
transferDbgValues(N1, OpOp);
return OpOp;
}
}
}
break;
case ISD::ZERO_EXTEND:
assert(VT.isInteger() && N1.getValueType().isInteger() &&
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24 changes: 12 additions & 12 deletions llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
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Expand Up @@ -37,19 +37,19 @@ define signext i8 @test_chars(i8 signext %c1, i8 signext %c2, i8 signext %c3, i8
; 32BIT: bb.0.entry:
; 32BIT-NEXT: liveins: $r3, $r4, $r5, $r6
; 32BIT-NEXT: {{ $}}
; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, killed renamable $r4
; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, killed renamable $r5
; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, killed renamable $r6
; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r4
; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r5
; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r6
; 32BIT-NEXT: renamable $r3 = EXTSB killed renamable $r3
; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $r3
;
; 64BIT-LABEL: name: test_chars
; 64BIT: bb.0.entry:
; 64BIT-NEXT: liveins: $x3, $x4, $x5, $x6
; 64BIT-NEXT: {{ $}}
; 64BIT-NEXT: renamable $r3 = ADD4 renamable $r3, renamable $r4, implicit killed $x4, implicit killed $x3
; 64BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, renamable $r5, implicit killed $x5
; 64BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, renamable $r6, implicit killed $x6, implicit-def $x3
; 64BIT-NEXT: renamable $r3 = nsw ADD4 renamable $r3, renamable $r4, implicit killed $x4, implicit killed $x3
; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r5, implicit killed $x5
; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r6, implicit killed $x6, implicit-def $x3
; 64BIT-NEXT: renamable $x3 = EXTSB8 killed renamable $x3
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
entry:
Expand Down Expand Up @@ -96,19 +96,19 @@ define signext i8 @test_chars_mix(i8 signext %c1, i8 zeroext %c2, i8 zeroext %c3
; 32BIT: bb.0.entry:
; 32BIT-NEXT: liveins: $r3, $r4, $r5, $r6
; 32BIT-NEXT: {{ $}}
; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, killed renamable $r4
; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, killed renamable $r5
; 32BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, killed renamable $r6
; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r4
; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r5
; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r6
; 32BIT-NEXT: renamable $r3 = EXTSB killed renamable $r3
; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $r3
;
; 64BIT-LABEL: name: test_chars_mix
; 64BIT: bb.0.entry:
; 64BIT-NEXT: liveins: $x3, $x4, $x5, $x6
; 64BIT-NEXT: {{ $}}
; 64BIT-NEXT: renamable $r3 = ADD4 renamable $r3, renamable $r4, implicit killed $x4, implicit killed $x3
; 64BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, renamable $r5, implicit killed $x5
; 64BIT-NEXT: renamable $r3 = ADD4 killed renamable $r3, renamable $r6, implicit killed $x6, implicit-def $x3
; 64BIT-NEXT: renamable $r3 = nsw ADD4 renamable $r3, renamable $r4, implicit killed $x4, implicit killed $x3
; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r5, implicit killed $x5
; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r6, implicit killed $x6, implicit-def $x3
; 64BIT-NEXT: renamable $x3 = EXTSB8 killed renamable $x3
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
entry:
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7 changes: 4 additions & 3 deletions llvm/test/CodeGen/X86/trunc-nsw-nuw.ll
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Expand Up @@ -62,10 +62,11 @@ entry:
define i32 @simplify_demanded_bits_drop_flag(i1 zeroext %x, i1 zeroext %y) nounwind {
; CHECK-LABEL: simplify_demanded_bits_drop_flag:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: negl %edi
; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
; CHECK-NEXT: shll $2, %esi
; CHECK-NEXT: xorl %edi, %esi
; CHECK-NEXT: movslq %esi, %rax
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: negq %rax
; CHECK-NEXT: xorq %rsi, %rax
; CHECK-NEXT: imulq $-1634202141, %rax, %rax # imm = 0x9E980DE3
; CHECK-NEXT: movq %rax, %rcx
; CHECK-NEXT: shrq $63, %rcx
Expand Down
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