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AMDGPU: Use Register type for isStackAccess #154320

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Merged
merged 1 commit into from
Aug 19, 2025
Merged

AMDGPU: Use Register type for isStackAccess #154320

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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -9229,7 +9229,7 @@ bool SIInstrInfo::isHighLatencyDef(int Opc) const {
(isMUBUF(Opc) || isMTBUF(Opc) || isMIMG(Opc) || isFLAT(Opc));
}

unsigned SIInstrInfo::isStackAccess(const MachineInstr &MI,
Register SIInstrInfo::isStackAccess(const MachineInstr &MI,
int &FrameIndex) const {
const MachineOperand *Addr = getNamedOperand(MI, AMDGPU::OpName::vaddr);
if (!Addr || !Addr->isFI())
Expand All @@ -9242,7 +9242,7 @@ unsigned SIInstrInfo::isStackAccess(const MachineInstr &MI,
return getNamedOperand(MI, AMDGPU::OpName::vdata)->getReg();
}

unsigned SIInstrInfo::isSGPRStackAccess(const MachineInstr &MI,
Register SIInstrInfo::isSGPRStackAccess(const MachineInstr &MI,
int &FrameIndex) const {
const MachineOperand *Addr = getNamedOperand(MI, AMDGPU::OpName::addr);
assert(Addr && Addr->isFI());
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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1407,8 +1407,8 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return get(pseudoToMCOpcode(Opcode));
}

unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
Register isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
Register isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;

Register isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
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