Mips: Force 64bit subtarget feature to be set for ABI options

[arsenm]

Prepare to use this with HwMode. This is mostly code copied from x86.

Mips has an exceptionally broken system where the target-abi option
can be used to change the pointer size. i.e., you can mix and match
32-bit base triples with an explicit request to use 32-bit or 64-bit
pointers such that you cannot rely on the triple reported pointer size.
This hack manages to only work for codegen. The MC subtarget constructors
do not have access to the target-abi name so those will continue to not
have the appropriate feature set.

[arsenm]

• Mips: Force 64bit subtarget feature to be set for ABI options #157446 👈 (View in Graphite)
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[llvmbot]

@llvm/pr-subscribers-backend-mips

Author: Matt Arsenault (arsenm)

Changes

Prepare to use this with HwMode. This is mostly code copied from x86.

Mips has an exceptionally broken system where the target-abi option
can be used to change the pointer size. i.e., you can mix and match
32-bit base triples with an explicit request to use 32-bit or 64-bit
pointers such that you cannot rely on the triple reported pointer size.
This hack manages to only work for codegen. The MC subtarget constructors
do not have access to the target-abi name so those will continue to not
have the appropriate feature set.

---

Full diff: https://github.com/llvm/llvm-project/pull/157446.diff

3 Files Affected:

• (modified) llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp (+10-1)
• (modified) llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h (+1)
• (modified) llvm/lib/Target/Mips/MipsSubtarget.cpp (+11-2)

diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
index 2cc634154bffd..c236c19cdb664 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
@@ -45,6 +45,10 @@ using namespace llvm;
 #define GET_REGINFO_MC_DESC
 #include "MipsGenRegisterInfo.inc"
 
+std::string MIPS_MC::ParseMIPSTriple(const Triple &TT) {
+  return TT.isMIPS64() ? "+ptr64" : "";
+}
+
 void MIPS_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
   // Mapping from CodeView to MC register id.
   static const struct {
@@ -165,7 +169,12 @@ static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
 static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
                                                   StringRef CPU, StringRef FS) {
   CPU = MIPS_MC::selectMipsCPU(TT, CPU);
-  return createMipsMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
+
+  std::string ArchFS = MIPS_MC::ParseMIPSTriple(TT);
+  if (!FS.empty())
+    ArchFS = (Twine(ArchFS) + "," + FS).str();
+
+  return createMipsMCSubtargetInfoImpl(TT, CPU, /*TuneCPU=*/CPU, ArchFS);
 }
 
 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
index f3e3e6e8d1073..eb81d24385bdd 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
@@ -57,6 +57,7 @@ createMipsELFObjectWriter(const Triple &TT, bool IsN32);
 std::unique_ptr<MCObjectTargetWriter> createMipsWinCOFFObjectWriter();
 
 namespace MIPS_MC {
+std::string ParseMIPSTriple(const Triple &TT);
 void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
 
 StringRef selectMipsCPU(const Triple &TT, StringRef CPU);
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp
index 8c4bb15a7e617..ce1b3056c178d 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -245,10 +245,19 @@ CodeGenOptLevel MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
 MipsSubtarget &
 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
                                                const TargetMachine &TM) {
-  StringRef CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
+  const Triple &TT = TM.getTargetTriple();
+  StringRef CPUName = MIPS_MC::selectMipsCPU(TT, CPU);
+
+  std::string FullFS;
+  if (getABI().ArePtrs64bit()) {
+    FullFS = "+ptr64";
+    if (!FS.empty())
+      FullFS = (Twine(FullFS) + "," + FS).str();
+  } else
+    FullFS = FS.str();
 
   // Parse features string.
-  ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
+  ParseSubtargetFeatures(CPUName, /*TuneCPU=*/CPUName, FullFS);
   // Initialize scheduling itinerary for the specified CPU.
   InstrItins = getInstrItineraryForCPU(CPUName);
 

[s-barannikov]

Perhaps those should not be features after all.

[arsenm]

Perhaps those should not be features after all.

They really shouldn't be, but the target features system is a mess and it helps to have all the targets do the same thing

[topperc]

LGTM