[RISCV] Merge ADDI and SIGN_EXTEND_INREG to ADDIW during selectSETCC. #162614
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That we can merge ADDI with its LHS to ADDIW if its LHS is a SIGN_EXTEND_INREG.
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@llvm/pr-subscribers-backend-risc-v Author: Jim Lin (tclin914) ChangesThat we can merge ADDI with its LHS to ADDIW if its LHS is a SIGN_EXTEND_INREG. Full diff: https://github.com/llvm/llvm-project/pull/162614.diff 7 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 437022f5cde9f..90857a3775c58 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3353,14 +3353,19 @@ bool RISCVDAGToDAGISel::selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal,
0);
return true;
}
- // If the RHS is [-2047,2048], we can use addi with -RHS to produce 0 if the
- // LHS is equal to the RHS and non-zero otherwise.
+ // If the RHS is [-2047,2048], we can use addi/addiw with -RHS to produce 0
+ // if the LHS is equal to the RHS and non-zero otherwise.
if (isInt<12>(CVal) || CVal == 2048) {
- Val = SDValue(
- CurDAG->getMachineNode(
- RISCV::ADDI, DL, N->getValueType(0), LHS,
- CurDAG->getSignedTargetConstant(-CVal, DL, N->getValueType(0))),
- 0);
+ unsigned Opc = RISCV::ADDI;
+ if (LHS.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ Opc = RISCV::ADDIW;
+ LHS = LHS.getOperand(0);
+ }
+
+ Val = SDValue(CurDAG->getMachineNode(Opc, DL, N->getValueType(0), LHS,
+ CurDAG->getSignedTargetConstant(
+ -CVal, DL, N->getValueType(0))),
+ 0);
return true;
}
if (isPowerOf2_64(CVal) && Subtarget->hasStdExtZbs()) {
diff --git a/llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll b/llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll
index 2a46a59e90535..4f036d3c991b9 100644
--- a/llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll
+++ b/llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll
@@ -221,8 +221,8 @@ define i64 @test12(i64 %0) #0 {
;
; RV64-LABEL: test12:
; RV64: # %bb.0: # %entry
-; RV64-NEXT: addiw a0, a0, -16
-; RV64-NEXT: addi a0, a0, 13
+; RV64-NEXT: addi a0, a0, -16
+; RV64-NEXT: addiw a0, a0, 13
; RV64-NEXT: seqz a0, a0
; RV64-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/i64-icmp.ll b/llvm/test/CodeGen/RISCV/i64-icmp.ll
index 88d989daaa5cd..2742b9a3655d3 100644
--- a/llvm/test/CodeGen/RISCV/i64-icmp.ll
+++ b/llvm/test/CodeGen/RISCV/i64-icmp.ll
@@ -708,8 +708,7 @@ define i64 @icmp_sle_constant_neg_2050(i64 %a) nounwind {
define i64 @icmp_eq_zext_inreg_small_constant(i64 %a) nounwind {
; RV64I-LABEL: icmp_eq_zext_inreg_small_constant:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: addi a0, a0, -123
+; RV64I-NEXT: addiw a0, a0, -123
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
%1 = and i64 %a, 4294967295
@@ -748,8 +747,7 @@ define i64 @icmp_ne_zext_inreg_small_constant(i64 %a) nounwind {
define i64 @icmp_ne_zext_inreg_large_constant(i64 %a) nounwind {
; RV64I-LABEL: icmp_ne_zext_inreg_large_constant:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: addi a0, a0, 2
+; RV64I-NEXT: addiw a0, a0, 2
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret
%1 = and i64 %a, 4294967295
diff --git a/llvm/test/CodeGen/RISCV/select-to-and-zext.ll b/llvm/test/CodeGen/RISCV/select-to-and-zext.ll
index 2f03ff969205f..318268a1e5fff 100644
--- a/llvm/test/CodeGen/RISCV/select-to-and-zext.ll
+++ b/llvm/test/CodeGen/RISCV/select-to-and-zext.ll
@@ -15,8 +15,7 @@ define i32 @from_cmpeq(i32 %xx, i32 %y) {
;
; RV64I-LABEL: from_cmpeq:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: addi a0, a0, -9
+; RV64I-NEXT: addiw a0, a0, -9
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
@@ -39,8 +38,7 @@ define i32 @from_cmpeq_fail_bad_andmask(i32 %xx, i32 %y) {
;
; RV64I-LABEL: from_cmpeq_fail_bad_andmask:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: addi a0, a0, -9
+; RV64I-NEXT: addiw a0, a0, -9
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a1, a0
diff --git a/llvm/test/CodeGen/RISCV/setcc-logic.ll b/llvm/test/CodeGen/RISCV/setcc-logic.ll
index fabb573e98d2a..4e14893290ca8 100644
--- a/llvm/test/CodeGen/RISCV/setcc-logic.ll
+++ b/llvm/test/CodeGen/RISCV/setcc-logic.ll
@@ -104,9 +104,8 @@ define i1 @and_icmps_const_not1bit_diff(i32 %x) nounwind {
;
; RV64I-LABEL: and_icmps_const_not1bit_diff:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: addi a1, a0, -44
-; RV64I-NEXT: addi a0, a0, -92
+; RV64I-NEXT: addiw a1, a0, -44
+; RV64I-NEXT: addiw a0, a0, -92
; RV64I-NEXT: snez a1, a1
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: and a0, a1, a0
diff --git a/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll b/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
index bdbe4ed216919..07bfbe65bd9e2 100644
--- a/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
+++ b/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
@@ -674,8 +674,7 @@ define i32 @sext_of_not_cmp_i32(i32 %x) {
;
; RV64-LABEL: sext_of_not_cmp_i32:
; RV64: # %bb.0:
-; RV64-NEXT: sext.w a0, a0
-; RV64-NEXT: addi a0, a0, -7
+; RV64-NEXT: addiw a0, a0, -7
; RV64-NEXT: seqz a0, a0
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: ret
@@ -718,8 +717,7 @@ define i32 @dec_of_zexted_cmp_i32(i32 %x) {
;
; RV64-LABEL: dec_of_zexted_cmp_i32:
; RV64: # %bb.0:
-; RV64-NEXT: sext.w a0, a0
-; RV64-NEXT: addi a0, a0, -7
+; RV64-NEXT: addiw a0, a0, -7
; RV64-NEXT: seqz a0, a0
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/xaluo.ll b/llvm/test/CodeGen/RISCV/xaluo.ll
index 2751332c9e3ae..bf6802deeffdc 100644
--- a/llvm/test/CodeGen/RISCV/xaluo.ll
+++ b/llvm/test/CodeGen/RISCV/xaluo.ll
@@ -1047,8 +1047,8 @@ define zeroext i1 @usubo.i32.constant.lhs(i32 signext %v1, ptr %res) {
; RV64-LABEL: usubo.i32.constant.lhs:
; RV64: # %bb.0: # %entry
; RV64-NEXT: li a2, -2
-; RV64-NEXT: subw a2, a2, a0
-; RV64-NEXT: addi a0, a2, 1
+; RV64-NEXT: sub a2, a2, a0
+; RV64-NEXT: addiw a0, a2, 1
; RV64-NEXT: seqz a0, a0
; RV64-NEXT: sw a2, 0(a1)
; RV64-NEXT: ret
@@ -1065,8 +1065,8 @@ define zeroext i1 @usubo.i32.constant.lhs(i32 signext %v1, ptr %res) {
; RV64ZBA-LABEL: usubo.i32.constant.lhs:
; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: li a2, -2
-; RV64ZBA-NEXT: subw a2, a2, a0
-; RV64ZBA-NEXT: addi a0, a2, 1
+; RV64ZBA-NEXT: sub a2, a2, a0
+; RV64ZBA-NEXT: addiw a0, a2, 1
; RV64ZBA-NEXT: seqz a0, a0
; RV64ZBA-NEXT: sw a2, 0(a1)
; RV64ZBA-NEXT: ret
@@ -1083,8 +1083,8 @@ define zeroext i1 @usubo.i32.constant.lhs(i32 signext %v1, ptr %res) {
; RV64ZICOND-LABEL: usubo.i32.constant.lhs:
; RV64ZICOND: # %bb.0: # %entry
; RV64ZICOND-NEXT: li a2, -2
-; RV64ZICOND-NEXT: subw a2, a2, a0
-; RV64ZICOND-NEXT: addi a0, a2, 1
+; RV64ZICOND-NEXT: sub a2, a2, a0
+; RV64ZICOND-NEXT: addiw a0, a2, 1
; RV64ZICOND-NEXT: seqz a0, a0
; RV64ZICOND-NEXT: sw a2, 0(a1)
; RV64ZICOND-NEXT: ret
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topperc
reviewed
Oct 9, 2025
akadutta
pushed a commit
to akadutta/llvm-project
that referenced
this pull request
Oct 14, 2025
…llvm#162614) That we can merge ADDI with its LHS to ADDIW if its LHS is a SIGN_EXTEND_INREG.
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That we can merge ADDI with its LHS to ADDIW if its LHS is a SIGN_EXTEND_INREG.