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[RISCV] Merge ADDI and SIGN_EXTEND_INREG to ADDIW during selectSETCC. #162614

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Merged
merged 2 commits into from
Oct 14, 2025
Merged

[RISCV] Merge ADDI and SIGN_EXTEND_INREG to ADDIW during selectSETCC. #162614

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2eb9554
[RISCV] Merge ADDI and SIGN_EXTEND_INREG to ADDIW during selectSETCC.
tclin914 Oct 9, 2025
14e90fb
Check the VT in operand 1 of the SIGN_EXTEND_INREG
tclin914 Oct 13, 2025
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20 changes: 13 additions & 7 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3353,14 +3353,20 @@ bool RISCVDAGToDAGISel::selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal,
0);
return true;
}
// If the RHS is [-2047,2048], we can use addi with -RHS to produce 0 if the
// LHS is equal to the RHS and non-zero otherwise.
// If the RHS is [-2047,2048], we can use addi/addiw with -RHS to produce 0
// if the LHS is equal to the RHS and non-zero otherwise.
if (isInt<12>(CVal) || CVal == 2048) {
Val = SDValue(
CurDAG->getMachineNode(
RISCV::ADDI, DL, N->getValueType(0), LHS,
CurDAG->getSignedTargetConstant(-CVal, DL, N->getValueType(0))),
0);
unsigned Opc = RISCV::ADDI;
if (LHS.getOpcode() == ISD::SIGN_EXTEND_INREG &&
cast<VTSDNode>(LHS.getOperand(1))->getVT() == MVT::i32) {
Opc = RISCV::ADDIW;
LHS = LHS.getOperand(0);
}

Val = SDValue(CurDAG->getMachineNode(Opc, DL, N->getValueType(0), LHS,
CurDAG->getSignedTargetConstant(
-CVal, DL, N->getValueType(0))),
0);
return true;
}
if (isPowerOf2_64(CVal) && Subtarget->hasStdExtZbs()) {
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll
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Expand Up @@ -221,8 +221,8 @@ define i64 @test12(i64 %0) #0 {
;
; RV64-LABEL: test12:
; RV64: # %bb.0: # %entry
; RV64-NEXT: addiw a0, a0, -16
; RV64-NEXT: addi a0, a0, 13
; RV64-NEXT: addi a0, a0, -16
; RV64-NEXT: addiw a0, a0, 13
; RV64-NEXT: seqz a0, a0
; RV64-NEXT: ret
entry:
Expand Down
6 changes: 2 additions & 4 deletions llvm/test/CodeGen/RISCV/i64-icmp.ll
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Expand Up @@ -708,8 +708,7 @@ define i64 @icmp_sle_constant_neg_2050(i64 %a) nounwind {
define i64 @icmp_eq_zext_inreg_small_constant(i64 %a) nounwind {
; RV64I-LABEL: icmp_eq_zext_inreg_small_constant:
; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: addi a0, a0, -123
; RV64I-NEXT: addiw a0, a0, -123
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
%1 = and i64 %a, 4294967295
Expand Down Expand Up @@ -748,8 +747,7 @@ define i64 @icmp_ne_zext_inreg_small_constant(i64 %a) nounwind {
define i64 @icmp_ne_zext_inreg_large_constant(i64 %a) nounwind {
; RV64I-LABEL: icmp_ne_zext_inreg_large_constant:
; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: addi a0, a0, 2
; RV64I-NEXT: addiw a0, a0, 2
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret
%1 = and i64 %a, 4294967295
Expand Down
6 changes: 2 additions & 4 deletions llvm/test/CodeGen/RISCV/select-to-and-zext.ll
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Expand Up @@ -15,8 +15,7 @@ define i32 @from_cmpeq(i32 %xx, i32 %y) {
;
; RV64I-LABEL: from_cmpeq:
; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: addi a0, a0, -9
; RV64I-NEXT: addiw a0, a0, -9
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
Expand All @@ -39,8 +38,7 @@ define i32 @from_cmpeq_fail_bad_andmask(i32 %xx, i32 %y) {
;
; RV64I-LABEL: from_cmpeq_fail_bad_andmask:
; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: addi a0, a0, -9
; RV64I-NEXT: addiw a0, a0, -9
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a1, a0
Expand Down
5 changes: 2 additions & 3 deletions llvm/test/CodeGen/RISCV/setcc-logic.ll
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Expand Up @@ -104,9 +104,8 @@ define i1 @and_icmps_const_not1bit_diff(i32 %x) nounwind {
;
; RV64I-LABEL: and_icmps_const_not1bit_diff:
; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: addi a1, a0, -44
; RV64I-NEXT: addi a0, a0, -92
; RV64I-NEXT: addiw a1, a0, -44
; RV64I-NEXT: addiw a0, a0, -92
; RV64I-NEXT: snez a1, a1
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: and a0, a1, a0
Expand Down
6 changes: 2 additions & 4 deletions llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
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Expand Up @@ -674,8 +674,7 @@ define i32 @sext_of_not_cmp_i32(i32 %x) {
;
; RV64-LABEL: sext_of_not_cmp_i32:
; RV64: # %bb.0:
; RV64-NEXT: sext.w a0, a0
; RV64-NEXT: addi a0, a0, -7
; RV64-NEXT: addiw a0, a0, -7
; RV64-NEXT: seqz a0, a0
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: ret
Expand Down Expand Up @@ -718,8 +717,7 @@ define i32 @dec_of_zexted_cmp_i32(i32 %x) {
;
; RV64-LABEL: dec_of_zexted_cmp_i32:
; RV64: # %bb.0:
; RV64-NEXT: sext.w a0, a0
; RV64-NEXT: addi a0, a0, -7
; RV64-NEXT: addiw a0, a0, -7
; RV64-NEXT: seqz a0, a0
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: ret
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/xaluo.ll
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Expand Up @@ -1047,8 +1047,8 @@ define zeroext i1 @usubo.i32.constant.lhs(i32 signext %v1, ptr %res) {
; RV64-LABEL: usubo.i32.constant.lhs:
; RV64: # %bb.0: # %entry
; RV64-NEXT: li a2, -2
; RV64-NEXT: subw a2, a2, a0
; RV64-NEXT: addi a0, a2, 1
; RV64-NEXT: sub a2, a2, a0
; RV64-NEXT: addiw a0, a2, 1
; RV64-NEXT: seqz a0, a0
; RV64-NEXT: sw a2, 0(a1)
; RV64-NEXT: ret
Expand All @@ -1065,8 +1065,8 @@ define zeroext i1 @usubo.i32.constant.lhs(i32 signext %v1, ptr %res) {
; RV64ZBA-LABEL: usubo.i32.constant.lhs:
; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: li a2, -2
; RV64ZBA-NEXT: subw a2, a2, a0
; RV64ZBA-NEXT: addi a0, a2, 1
; RV64ZBA-NEXT: sub a2, a2, a0
; RV64ZBA-NEXT: addiw a0, a2, 1
; RV64ZBA-NEXT: seqz a0, a0
; RV64ZBA-NEXT: sw a2, 0(a1)
; RV64ZBA-NEXT: ret
Expand All @@ -1083,8 +1083,8 @@ define zeroext i1 @usubo.i32.constant.lhs(i32 signext %v1, ptr %res) {
; RV64ZICOND-LABEL: usubo.i32.constant.lhs:
; RV64ZICOND: # %bb.0: # %entry
; RV64ZICOND-NEXT: li a2, -2
; RV64ZICOND-NEXT: subw a2, a2, a0
; RV64ZICOND-NEXT: addi a0, a2, 1
; RV64ZICOND-NEXT: sub a2, a2, a0
; RV64ZICOND-NEXT: addiw a0, a2, 1
; RV64ZICOND-NEXT: seqz a0, a0
; RV64ZICOND-NEXT: sw a2, 0(a1)
; RV64ZICOND-NEXT: ret
Expand Down