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[RISCV] Remove untested Zvfbfmin isel patterns #164111
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These were added with the Zvfbfa instrinsics but aren't tested. We should probably have these patterns but they should be applicable to Zvfbfmin and Zvbfa and would need to be tested.
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesThese were added with the Zvfbfa instrinsics but aren't tested. We should probably have these patterns but they should be applicable to Zvfbfmin and Zvbfa and would need to be tested. Full diff: https://github.com/llvm/llvm-project/pull/164111.diff 1 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
index 9358486c13da2..88adb29731907 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
@@ -475,20 +475,6 @@ let Predicates = [HasStdExtZvfbfmin] in {
fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask VMV0:$vm),
fvti.AVL, fvti.Log2SEW)>;
- def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm),
- (SplatFPOp (SelectScalarFPAsInt (XLenVT GPR:$imm))),
- fvti.RegClass:$rs2)),
- (!cast<Instruction>("PseudoVMERGE_VXM_"#fvti.LMul.MX)
- (fvti.Vector (IMPLICIT_DEF)),
- fvti.RegClass:$rs2, GPR:$imm, (fvti.Mask VMV0:$vm), fvti.AVL, fvti.Log2SEW)>;
-
- def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm),
- (SplatFPOp (fvti.Scalar fpimm0)),
- fvti.RegClass:$rs2)),
- (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX)
- (fvti.Vector (IMPLICIT_DEF)),
- fvti.RegClass:$rs2, 0, (fvti.Mask VMV0:$vm), fvti.AVL, fvti.Log2SEW)>;
-
def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm),
(SplatFPOp fvti.ScalarRegClass:$rs1),
fvti.RegClass:$rs2)),
@@ -507,25 +493,6 @@ let Predicates = [HasStdExtZvfbfmin] in {
fvti.RegClass:$passthru, fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask VMV0:$vm),
GPR:$vl, fvti.Log2SEW)>;
- def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask VMV0:$vm),
- (SplatFPOp (SelectScalarFPAsInt (XLenVT GPR:$imm))),
- fvti.RegClass:$rs2,
- fvti.RegClass:$passthru,
- VLOpFrag)),
- (!cast<Instruction>("PseudoVMERGE_VXM_"#fvti.LMul.MX)
- fvti.RegClass:$passthru, fvti.RegClass:$rs2, GPR:$imm, (fvti.Mask VMV0:$vm),
- GPR:$vl, fvti.Log2SEW)>;
-
-
- def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask VMV0:$vm),
- (SplatFPOp (fvti.Scalar fpimm0)),
- fvti.RegClass:$rs2,
- fvti.RegClass:$passthru,
- VLOpFrag)),
- (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX)
- fvti.RegClass:$passthru, fvti.RegClass:$rs2, 0, (fvti.Mask VMV0:$vm),
- GPR:$vl, fvti.Log2SEW)>;
-
def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask VMV0:$vm),
(SplatFPOp fvti.ScalarRegClass:$rs1),
fvti.RegClass:$rs2,
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4vtomat
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LGTM~
tclin914
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LGTM
These were added with the Zvfbfa instrinsics but aren't tested. We should probably have these patterns but they should be applicable to Zvfbfmin and Zvbfa and would need to be tested.
These were added with the Zvfbfa instrinsics but aren't tested. We should probably have these patterns but they should be applicable to Zvfbfmin and Zvbfa and would need to be tested.
These were added with the Zvfbfa instrinsics but aren't tested. We should probably have these patterns but they should be applicable to Zvfbfmin and Zvbfa and would need to be tested.