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[Hexagon] Handle truncate of v64i32 -> v64i1 when Hvx is enabled #164931

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Merged
merged 1 commit into from
Oct 31, 2025
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[Hexagon] Handle truncate of v64i32 -> v64i1 when Hvx is enabled #164931

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3 changes: 3 additions & 0 deletions llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
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Original file line number Diff line number Diff line change
Expand Up @@ -612,6 +612,9 @@ let Predicates = [UseHVX] in {
(V6_vandvrt HvxVR:$Vs, (ToI32 0x01010101))>;
def: Pat<(VecQ32 (trunc HVI32:$Vs)),
(V6_vandvrt HvxVR:$Vs, (ToI32 0x01010101))>;
def: Pat<(VecQ16 (trunc HWI32:$Vss)),
(Combineq(VecQ32(V6_vandvrt (HiVec $Vss), (ToI32 0x01010101))),
(VecQ32 (V6_vandvrt (LoVec $Vss), (ToI32 0x01010101))))>;
}

let Predicates = [UseHVX] in {
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18 changes: 18 additions & 0 deletions llvm/test/CodeGen/Hexagon/isel/trunc-vNi1-HVX.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,18 @@
; RUN: llc --mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s | FileCheck %s

define void @f5(<64 x i32> %a0, ptr %a1) {
; CHECK-LABEL: f5:
; CHECK: [[REG0:(r[0-9]+)]] = ##16843009
; CHECK-DAG: q[[Q0:[0-9]+]] = vand(v{{[0-9]+}},[[REG0]])
; CHECK-DAG: q[[Q1:[0-9]+]] = vand(v{{[0-9]+}},[[REG0]])
; CHECK: v{{[0-9]+}}.b = vpacke(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
; CHECK: v{{[0-9]+}}.b = vpacke(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
; CHECK: v[[VROR:[0-9]+]] = vror(v{{[0-9]+}},r{{[0-9]+}})
; CHECK: v[[VOR:[0-9]+]] = vor(v[[VROR]],v{{[0-9]+}})
; CHECK: q{{[0-9]+}} = vand(v[[VOR]],r{{[0-9]+}})
b0:
%v0 = trunc <64 x i32> %a0 to <64 x i1>
store <64 x i1> %v0, ptr %a1, align 1
ret void
}