Skip to content

[AArch64] Combine subtract with borrow to SBC. #165271

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 2 commits into
base: main
Choose a base branch
from
+425 −0
Open

[AArch64] Combine subtract with borrow to SBC. #165271

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
77ed715
Add tests.
rj-jesus Oct 24, 2025
4cbc151
[AArch64] Combine subtract with borrow to SBC.
rj-jesus Oct 24, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
33 changes: 33 additions & 0 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -22328,6 +22328,37 @@ static SDValue performExtBinopLoadFold(SDNode *N, SelectionDAG &DAG) {
return DAG.getNode(N->getOpcode(), DL, VT, Ext0, NShift);
}

// Attempt to combine the following patterns:
// SUB x, (CSET LO, (CMP a, b)) -> SBC x, 0, (CMP a, b)
// SUB (SUB x, y), (CSET LO, (CMP a, b)) -> SBC x, y, (CMP a, b)
// The CSET may be preceded by a ZEXT.
static SDValue performSubWithBorrowCombine(SDNode *N, SelectionDAG &DAG) {
if (N->getOpcode() != ISD::SUB)
return SDValue();

EVT VT = N->getValueType(0);
if (VT != MVT::i32 && VT != MVT::i64)
return SDValue();

SDValue N1 = N->getOperand(1);
if (N1.getOpcode() == ISD::ZERO_EXTEND && N1.hasOneUse())
N1 = N1.getOperand(0);
if (!N1.hasOneUse() || getCSETCondCode(N1) != AArch64CC::LO)
return SDValue();

SDValue Flags = N1.getOperand(3);
if (Flags.getOpcode() != AArch64ISD::SUBS)
return SDValue();

SDLoc DL(N);
SDValue N0 = N->getOperand(0);
if (N0->getOpcode() != ISD::SUB)
return DAG.getNode(AArch64ISD::SBC, DL, VT, N0, DAG.getConstant(0, DL, VT),
Flags);
return DAG.getNode(AArch64ISD::SBC, DL, VT, N0.getOperand(0),
N0.getOperand(1), Flags);
Comment on lines +22358 to +22359
Copy link
Contributor Author

@rj-jesus rj-jesus Oct 27, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This could be a separate combine. I kept it here as it didn't seem to affect existing tests (other than the ones in this PR), but I'm happy to implement it separately if that's preferable.

}

static SDValue performAddSubCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI) {
// Try to change sum of two reductions.
Expand All @@ -22349,6 +22380,8 @@ static SDValue performAddSubCombine(SDNode *N,
return Val;
if (SDValue Val = performAddSubIntoVectorOp(N, DCI.DAG))
return Val;
if (SDValue Val = performSubWithBorrowCombine(N, DCI.DAG))
return Val;

if (SDValue Val = performExtBinopLoadFold(N, DCI.DAG))
return Val;
Expand Down
Loading