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[AArch64][GlobalISel] SIMD fpcvt codegen for rounding nodes #165546

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[AArch64][GlobalISel] SIMD fpcvt codegen for rounding nodes #165546

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6377946
[AArch64][GlobalISel] SIMD fpcvt codegen for rounding nodes
Lukacma Oct 29, 2025
cec5513
Merge branch 'llvm:main' into cvt-round
Lukacma Oct 29, 2025
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73 changes: 73 additions & 0 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -6799,6 +6799,79 @@ defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, fp_to_uint_sat_gi, ftrunc, "F
defm : FPToIntegerPats<fp_to_sint, fp_to_sint_sat, fp_to_sint_sat_gi, fround, "FCVTAS">;
defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, fp_to_uint_sat_gi, fround, "FCVTAU">;

// For global-isel we can use register classes to determine
// which FCVT instruction to use.
let Predicates = [HasFPRCVT] in {
def : Pat<(i64 (any_lround f32:$Rn)),
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@CarolineConcatto CarolineConcatto Oct 31, 2025

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Should we not add pattern for the GlobalISel too. It seams to me that all the tests are always falling back to the selection dag.

(FCVTASDSr f32:$Rn)>;
def : Pat<(i64 (any_llround f32:$Rn)),
(FCVTASDSr f32:$Rn)>;
}
def : Pat<(i64 (any_lround f64:$Rn)),
(FCVTASv1i64 f64:$Rn)>;
def : Pat<(i64 (any_llround f64:$Rn)),
(FCVTASv1i64 f64:$Rn)>;

let Predicates = [HasFPRCVT] in {
def : Pat<(f32 (bitconvert (i32 (any_lround f16:$Rn)))),
(FCVTASSHr f16:$Rn)>;
def : Pat<(f64 (bitconvert (i64 (any_lround f16:$Rn)))),
(FCVTASDHr f16:$Rn)>;
def : Pat<(f64 (bitconvert (i64 (any_llround f16:$Rn)))),
(FCVTASDHr f16:$Rn)>;
def : Pat<(f64 (bitconvert (i64 (any_lround f32:$Rn)))),
(FCVTASDSr f32:$Rn)>;
def : Pat<(f32 (bitconvert (i32 (any_lround f64:$Rn)))),
(FCVTASSDr f64:$Rn)>;
def : Pat<(f64 (bitconvert (i64 (any_llround f32:$Rn)))),
(FCVTASDSr f32:$Rn)>;
}
def : Pat<(f32 (bitconvert (i32 (any_lround f32:$Rn)))),
(FCVTASv1i32 f32:$Rn)>;
def : Pat<(f64 (bitconvert (i64 (any_lround f64:$Rn)))),
(FCVTASv1i64 f64:$Rn)>;
def : Pat<(f64 (bitconvert (i64 (any_llround f64:$Rn)))),
(FCVTASv1i64 f64:$Rn)>;

// For global-isel we can use register classes to determine
// which FCVT instruction to use.
let Predicates = [HasFPRCVT] in {
def : Pat<(i64 (any_lrint f16:$Rn)),
(FCVTZSDHr (FRINTXHr f16:$Rn))>;
def : Pat<(i64 (any_llrint f16:$Rn)),
(FCVTZSDHr (FRINTXHr f16:$Rn))>;
def : Pat<(i64 (any_lrint f32:$Rn)),
(FCVTZSDSr (FRINTXSr f32:$Rn))>;
def : Pat<(i64 (any_llrint f32:$Rn)),
(FCVTZSDSr (FRINTXSr f32:$Rn))>;
}
def : Pat<(i64 (any_lrint f64:$Rn)),
(FCVTZSv1i64 (FRINTXDr f64:$Rn))>;
def : Pat<(i64 (any_llrint f64:$Rn)),
(FCVTZSv1i64 (FRINTXDr f64:$Rn))>;

let Predicates = [HasFPRCVT] in {
def : Pat<(f32 (bitconvert (i32 (any_lrint f16:$Rn)))),
(FCVTZSSHr (FRINTXHr f16:$Rn))>;
def : Pat<(f64 (bitconvert (i64 (any_lrint f16:$Rn)))),
(FCVTZSDHr (FRINTXHr f16:$Rn))>;
def : Pat<(f64 (bitconvert (i64 (any_llrint f16:$Rn)))),
(FCVTZSDHr (FRINTXHr f16:$Rn))>;
def : Pat<(f64 (bitconvert (i64 (any_lrint f32:$Rn)))),
(FCVTZSDSr (FRINTXSr f32:$Rn))>;
def : Pat<(f32 (bitconvert (i32 (any_lrint f64:$Rn)))),
(FCVTZSSDr (FRINTXDr f64:$Rn))>;
def : Pat<(f64 (bitconvert (i64 (any_llrint f32:$Rn)))),
(FCVTZSDSr (FRINTXSr f32:$Rn))>;
}
def : Pat<(f32 (bitconvert (i32 (any_lrint f32:$Rn)))),
(FCVTZSv1i32 (FRINTXSr f32:$Rn))>;
def : Pat<(f64 (bitconvert (i64 (any_lrint f64:$Rn)))),
(FCVTZSv1i64 (FRINTXDr f64:$Rn))>;
def : Pat<(f64 (bitconvert (i64 (any_llrint f64:$Rn)))),
(FCVTZSv1i64 (FRINTXDr f64:$Rn))>;


// f16 -> s16 conversions
let Predicates = [HasFullFP16] in {
def : Pat<(i16(fp_to_sint_sat_gi f16:$Rn)), (FCVTZSv1f16 f16:$Rn)>;
Expand Down
18 changes: 5 additions & 13 deletions llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
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Expand Up @@ -858,7 +858,11 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_FPTOSI_SAT:
case TargetOpcode::G_FPTOUI_SAT:
case TargetOpcode::G_FPTOSI:
case TargetOpcode::G_FPTOUI: {
case TargetOpcode::G_FPTOUI:
case TargetOpcode::G_INTRINSIC_LRINT:
case TargetOpcode::G_INTRINSIC_LLRINT:
case TargetOpcode::G_LROUND:
case TargetOpcode::G_LLROUND: {
Comment on lines +861 to +865
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@arsenm arsenm Nov 1, 2025

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All of the changes seem to be for the non-strictfp case

LLT DstType = MRI.getType(MI.getOperand(0).getReg());
if (DstType.isVector())
break;
Expand All @@ -879,12 +883,6 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
break;
}
case TargetOpcode::G_INTRINSIC_LRINT:
case TargetOpcode::G_INTRINSIC_LLRINT:
if (MRI.getType(MI.getOperand(0).getReg()).isVector())
break;
OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
break;
case TargetOpcode::G_FCMP: {
// If the result is a vector, it must use a FPR.
AArch64GenRegisterBankInfo::PartialMappingIdx Idx0 =
Expand Down Expand Up @@ -1224,12 +1222,6 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
}
break;
}
case TargetOpcode::G_LROUND:
case TargetOpcode::G_LLROUND: {
// Source is always floating point and destination is always integer.
OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
break;
}
}

// Finally construct the computed mapping.
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir
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Expand Up @@ -14,7 +14,7 @@ body: |
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %fpr:fpr(s64) = COPY $d0
; CHECK-NEXT: %llround:gpr(s64) = G_LLROUND %fpr(s64)
; CHECK-NEXT: %llround:fpr(s64) = G_LLROUND %fpr(s64)
; CHECK-NEXT: $d0 = COPY %llround(s64)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%fpr:_(s64) = COPY $d0
Expand All @@ -35,7 +35,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %gpr:gpr(s64) = COPY $x0
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY %gpr(s64)
; CHECK-NEXT: %llround:gpr(s64) = G_LLROUND [[COPY]](s64)
; CHECK-NEXT: %llround:fpr(s64) = G_LLROUND [[COPY]](s64)
; CHECK-NEXT: $d0 = COPY %llround(s64)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%gpr:_(s64) = COPY $x0
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/GlobalISel/regbank-lround.mir
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Expand Up @@ -14,7 +14,7 @@ body: |
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %fpr:fpr(s64) = COPY $d0
; CHECK-NEXT: %lround:gpr(s64) = G_LROUND %fpr(s64)
; CHECK-NEXT: %lround:fpr(s64) = G_LROUND %fpr(s64)
; CHECK-NEXT: $d0 = COPY %lround(s64)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%fpr:_(s64) = COPY $d0
Expand All @@ -35,7 +35,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %gpr:gpr(s64) = COPY $x0
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY %gpr(s64)
; CHECK-NEXT: %lround:gpr(s64) = G_LROUND [[COPY]](s64)
; CHECK-NEXT: %lround:fpr(s64) = G_LROUND [[COPY]](s64)
; CHECK-NEXT: $d0 = COPY %lround(s64)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%gpr:_(s64) = COPY $x0
Expand Down
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