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[doc][RISCV] Add XSfvfexp* and XSfvfexpa* into RISCVUsage.rst #166198

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[doc][RISCV] Add XSfvfexp* and XSfvfexpa* into RISCVUsage.rst #166198

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6 changes: 6 additions & 0 deletions llvm/docs/RISCVUsage.rst
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Expand Up @@ -406,6 +406,12 @@ The current vendor extensions supported are:
``XSfvcp``
LLVM implements `version 1.1.0 of the SiFive Vector Coprocessor Interface (VCIX) Software Specification <https://sifive.cdn.prismic.io/sifive/Zn3m1R5LeNNTwnLS_vcix-spec-software-v1p1.pdf>`__ by SiFive. All instructions are prefixed with `sf.vc.` as described in the specification, and the riscv-toolchain-convention document linked above.

``Xsfvfexp16e``, ``Xsfvfbfexp16e``, and ``Xsfvfexp32e``
LLVM implements `version 0.5 of the Vector Exponential Extension Specification <https://www.sifive.com/document-file/exponential-function-instruction-xsfvfexp32e-xsfvf>`__ by SiFive. All instructions are prefixed with `sf.` as described in the specification linked above.

``Xsfvfexpa`` and ``Xsfvfexpa64e``
LLVM implements `version 0.2 of the Vector Exponential Approximation Extension Specification <https://www.sifive.com/document-file/exponential-approximation-instruction-xsfvfexpa-ex>`__ by SiFive. All instructions are prefixed with `sf.` as described in the specification linked above.

``XSfvqmaccdod``, ``XSfvqmaccqoq``
LLVM implements `version 1.1.0 of the SiFive Int8 Matrix Multiplication Extensions Specification <https://sifive.cdn.prismic.io/sifive/1a2ad85b-d818-49f7-ba83-f51f1731edbe_int8-matmul-spec.pdf>`__ by SiFive. All instructions are prefixed with `sf.` as described in the specification linked above.

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