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[AMDGPU][NFC] Avoid copying MachineOperands #166293

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Merged
merged 1 commit into from
Nov 5, 2025
Merged

[AMDGPU][NFC] Avoid copying MachineOperands #166293

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6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6753,7 +6753,7 @@ bool AMDGPUInstructionSelector::selectSGetBarrierState(
MachineInstr &I, Intrinsic::ID IntrID) const {
MachineBasicBlock *MBB = I.getParent();
const DebugLoc &DL = I.getDebugLoc();
MachineOperand BarOp = I.getOperand(2);
const MachineOperand &BarOp = I.getOperand(2);
std::optional<int64_t> BarValImm =
getIConstantVRegSExtVal(BarOp.getReg(), *MRI);

Expand Down Expand Up @@ -6806,8 +6806,8 @@ bool AMDGPUInstructionSelector::selectNamedBarrierInit(
MachineInstr &I, Intrinsic::ID IntrID) const {
MachineBasicBlock *MBB = I.getParent();
const DebugLoc &DL = I.getDebugLoc();
MachineOperand BarOp = I.getOperand(1);
MachineOperand CntOp = I.getOperand(2);
const MachineOperand &BarOp = I.getOperand(1);
const MachineOperand &CntOp = I.getOperand(2);

// BarID = (BarOp >> 4) & 0x3F
Register TmpReg0 = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp
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Expand Up @@ -136,7 +136,7 @@ bool GCNPreRAOptimizationsImpl::processReg(Register Reg) {
continue;

if (Def.getOpcode() == AMDGPU::V_ACCVGPR_WRITE_B32_e64) {
MachineOperand DefSrcMO = Def.getOperand(1);
const MachineOperand &DefSrcMO = Def.getOperand(1);

// Immediates are not an issue and can be propagated in
// postrapseudos pass. Only handle cases where defining
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Expand Up @@ -7945,7 +7945,7 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
}
legalizeOperands(*NewInstr, MDT);
int SCCIdx = Inst.findRegisterDefOperandIdx(AMDGPU::SCC, /*TRI=*/nullptr);
MachineOperand SCCOp = Inst.getOperand(SCCIdx);
const MachineOperand &SCCOp = Inst.getOperand(SCCIdx);
addSCCDefUsersToVALUWorklist(SCCOp, Inst, Worklist, CondReg);
Inst.eraseFromParent();
return;
Expand Down Expand Up @@ -7985,7 +7985,7 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
legalizeOperandsVALUt16(*NewInstr, MRI);
legalizeOperands(*NewInstr, MDT);
int SCCIdx = Inst.findRegisterDefOperandIdx(AMDGPU::SCC, /*TRI=*/nullptr);
MachineOperand SCCOp = Inst.getOperand(SCCIdx);
const MachineOperand &SCCOp = Inst.getOperand(SCCIdx);
addSCCDefUsersToVALUWorklist(SCCOp, Inst, Worklist, CondReg);
Inst.eraseFromParent();
return;
Expand Down Expand Up @@ -8183,7 +8183,7 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
AMDGPU::OpName::src0_modifiers) >= 0)
NewInstr.addImm(0);
if (AMDGPU::hasNamedOperand(NewOpcode, AMDGPU::OpName::src0)) {
MachineOperand Src = Inst.getOperand(1);
const MachineOperand &Src = Inst.getOperand(1);
NewInstr->addOperand(Src);
}

Expand Down Expand Up @@ -9199,7 +9199,7 @@ void SIInstrInfo::movePackToVALU(SIInstrWorklist &Worklist,
addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
}

void SIInstrInfo::addSCCDefUsersToVALUWorklist(MachineOperand &Op,
void SIInstrInfo::addSCCDefUsersToVALUWorklist(const MachineOperand &Op,
MachineInstr &SCCDefInst,
SIInstrWorklist &Worklist,
Register NewCond) const {
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIInstrInfo.h
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Expand Up @@ -172,7 +172,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
void addUsersToMoveToVALUWorklist(Register Reg, MachineRegisterInfo &MRI,
SIInstrWorklist &Worklist) const;

void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
void addSCCDefUsersToVALUWorklist(const MachineOperand &Op,
MachineInstr &SCCDefInst,
SIInstrWorklist &Worklist,
Register NewCond = Register()) const;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
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Expand Up @@ -640,7 +640,7 @@ void SIPreEmitPeephole::collectUnpackingCandidates(
}

void SIPreEmitPeephole::performF32Unpacking(MachineInstr &I) {
MachineOperand DstOp = I.getOperand(0);
const MachineOperand &DstOp = I.getOperand(0);

uint16_t UnpackedOpcode = mapToUnpackedOpcode(I);
assert(UnpackedOpcode != std::numeric_limits<uint16_t>::max() &&
Expand Down
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