[AArch64] Add SimplifyDemandedVectorEltsForTargetNode support for AArch64ISD::DUPLANE nodes

[Red-RobinHood]

Fixes #87497

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[llvmbot]

@llvm/pr-subscribers-backend-aarch64

Author: None (Red-RobinHood)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/167177.diff

2 Files Affected:

• (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+32)
• (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.h (+7)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index c8a038fa99b30..7604cdc786268 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -31527,6 +31527,38 @@ bool AArch64TargetLowering::SimplifyDemandedBitsForTargetNode(
       Op, OriginalDemandedBits, OriginalDemandedElts, Known, TLO, Depth);
 }
 
+bool AArch64TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
+    SDValue Op,
+    const APInt &DemandedElts,
+    APInt &KnownUndef,
+    APInt &KnownZero,
+    TargetLoweringOpt &TLO,
+    unsigned Depth) const {
+
+  SDNode *N = Op.getNode();
+  unsigned Opc = N->getOpcode();
+
+  if (Opc != AArch64ISD::DUPLANE8 &&
+      Opc != AArch64ISD::DUPLANE16 &&
+      Opc != AArch64ISD::DUPLANE32 &&
+      Opc != AArch64ISD::DUPLANE64)
+    return false;
+
+  if (DemandedElts.popcount() != 1)
+  return false;
+
+  SDValue Src  = N->getOperand(0);
+  SDValue Lane = N->getOperand(1);
+
+  SDLoc DL(N);
+  SelectionDAG &DAG = TLO.DAG;
+
+  SDValue Extracted = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Src.getValueType().getScalarType(), Src, Lane);
+  SDValue Splat = DAG.getSplatVector(Op.getValueType(), DL, Extracted);
+
+  return TLO.CombineTo(Op, Splat);
+}
+
 bool AArch64TargetLowering::canCreateUndefOrPoisonForTargetNode(
     SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
     bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const {
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 70bfae717fb76..6cd26fe871a60 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -880,6 +880,13 @@ class AArch64TargetLowering : public TargetLowering {
                                          TargetLoweringOpt &TLO,
                                          unsigned Depth) const override;
 
+  bool SimplifyDemandedVectorEltsForTargetNode(SDValue Op,
+                                          const APInt &DemandedElts,
+                                          APInt &KnownUndef,
+                                          APInt &KnownZero,
+                                          TargetLoweringOpt &TLO,
+                                          unsigned Depth) const override;
+
   bool canCreateUndefOrPoisonForTargetNode(SDValue Op,
                                            const APInt &DemandedElts,
                                            const SelectionDAG &DAG,

[github-actions]

⚠️ C/C++ code formatter, clang-format found issues in your code. ⚠️

You can test this locally with the following command:

git-clang-format --diff origin/main HEAD --extensions h,cpp -- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.h --diff_from_common_commit

⚠️
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing origin/main to the base branch/commit you want to compare against.
⚠️

View the diff from clang-format here.

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 7604cdc78..b0bdc6b9a 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -31528,32 +31528,28 @@ bool AArch64TargetLowering::SimplifyDemandedBitsForTargetNode(
 }
 
 bool AArch64TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
-    SDValue Op,
-    const APInt &DemandedElts,
-    APInt &KnownUndef,
-    APInt &KnownZero,
-    TargetLoweringOpt &TLO,
-    unsigned Depth) const {
+    SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero,
+    TargetLoweringOpt &TLO, unsigned Depth) const {
 
   SDNode *N = Op.getNode();
   unsigned Opc = N->getOpcode();
 
-  if (Opc != AArch64ISD::DUPLANE8 &&
-      Opc != AArch64ISD::DUPLANE16 &&
-      Opc != AArch64ISD::DUPLANE32 &&
-      Opc != AArch64ISD::DUPLANE64)
+  if (Opc != AArch64ISD::DUPLANE8 && Opc != AArch64ISD::DUPLANE16 &&
+      Opc != AArch64ISD::DUPLANE32 && Opc != AArch64ISD::DUPLANE64)
     return false;
 
   if (DemandedElts.popcount() != 1)
-  return false;
+    return false;
 
-  SDValue Src  = N->getOperand(0);
+  SDValue Src = N->getOperand(0);
   SDValue Lane = N->getOperand(1);
 
   SDLoc DL(N);
   SelectionDAG &DAG = TLO.DAG;
 
-  SDValue Extracted = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Src.getValueType().getScalarType(), Src, Lane);
+  SDValue Extracted =
+      DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
+                  Src.getValueType().getScalarType(), Src, Lane);
   SDValue Splat = DAG.getSplatVector(Op.getValueType(), DL, Extracted);
 
   return TLO.CombineTo(Op, Splat);
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 6cd26fe87..ee6863528 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -880,12 +880,9 @@ private:
                                          TargetLoweringOpt &TLO,
                                          unsigned Depth) const override;
 
-  bool SimplifyDemandedVectorEltsForTargetNode(SDValue Op,
-                                          const APInt &DemandedElts,
-                                          APInt &KnownUndef,
-                                          APInt &KnownZero,
-                                          TargetLoweringOpt &TLO,
-                                          unsigned Depth) const override;
+  bool SimplifyDemandedVectorEltsForTargetNode(
+      SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
+      APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth) const override;
 
   bool canCreateUndefOrPoisonForTargetNode(SDValue Op,
                                            const APInt &DemandedElts,

[MacDue]

This needs formatting (with clang-format) and some tests

[Red-RobinHood]

Am I bit overwhelmed right now with some work. Will see to it in about a week.