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[CodeGen] Use MCRegUnit in two more TRI methods (NFC) #167680
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@llvm/pr-subscribers-tablegen @llvm/pr-subscribers-backend-amdgpu Author: Sergei Barannikov (s-barannikov) ChangesFull diff: https://github.com/llvm/llvm-project/pull/167680.diff 5 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 992d5a50a8bbf..dabf0dc5ec173 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -958,7 +958,7 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo {
TypeSize getRegSizeInBits(Register Reg, const MachineRegisterInfo &MRI) const;
/// Get the weight in units of pressure for this register unit.
- virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
+ virtual unsigned getRegUnitWeight(MCRegUnit RegUnit) const = 0;
/// Get the number of dimensions of register pressure.
virtual unsigned getNumRegPressureSets() const = 0;
@@ -978,7 +978,7 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo {
/// Get the dimensions of register pressure impacted by this register unit.
/// Returns a -1 terminated array of pressure set IDs.
- virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
+ virtual const int *getRegUnitPressureSets(MCRegUnit RegUnit) const = 0;
/// Get the scale factor of spill weight for this register class.
virtual float getSpillWeightScaleFactor(const TargetRegisterClass *RC) const;
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index ad79bdf3190f0..ecf3aee6048cd 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3781,7 +3781,7 @@ unsigned SIRegisterInfo::getRegPressureSetLimit(const MachineFunction &MF,
llvm_unreachable("Unexpected register pressure set!");
}
-const int *SIRegisterInfo::getRegUnitPressureSets(unsigned RegUnit) const {
+const int *SIRegisterInfo::getRegUnitPressureSets(MCRegUnit RegUnit) const {
static const int Empty[] = { -1 };
if (RegPressureIgnoredUnits[RegUnit])
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 813f6bb1a503a..cd4dc9bc4d037 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -357,7 +357,7 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
const MachineFunction &MF, const VirtRegMap *VRM,
const LiveRegMatrix *Matrix) const override;
- const int *getRegUnitPressureSets(unsigned RegUnit) const override;
+ const int *getRegUnitPressureSets(MCRegUnit RegUnit) const override;
MCRegister getReturnAddressReg(const MachineFunction &MF) const;
diff --git a/llvm/unittests/CodeGen/MFCommon.inc b/llvm/unittests/CodeGen/MFCommon.inc
index 783267aa05b59..23379dea0ded5 100644
--- a/llvm/unittests/CodeGen/MFCommon.inc
+++ b/llvm/unittests/CodeGen/MFCommon.inc
@@ -45,7 +45,7 @@ public:
static RegClassWeight Bogus{1, 16};
return Bogus;
}
- unsigned getRegUnitWeight(unsigned RegUnit) const override { return 1; }
+ unsigned getRegUnitWeight(MCRegUnit RegUnit) const override { return 1; }
unsigned getNumRegPressureSets() const override { return 0; }
const char *getRegPressureSetName(unsigned Idx) const override {
return "bogus";
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index 3e6e23ffec115..eac908d9bc2bd 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -234,9 +234,9 @@ void RegisterInfoEmitter::EmitRegUnitPressure(raw_ostream &OS,
}
OS << "/// Get the weight in units of pressure for this register unit.\n"
<< "unsigned " << ClassName << "::\n"
- << "getRegUnitWeight(unsigned RegUnit) const {\n"
- << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
- << " && \"invalid register unit\");\n";
+ << "getRegUnitWeight(MCRegUnit RegUnit) const {\n"
+ << " assert(static_cast<unsigned>(RegUnit) < "
+ << RegBank.getNumNativeRegUnits() << " && \"invalid register unit\");\n";
if (!RegUnitsHaveUnitWeight) {
OS << " static const uint8_t RUWeightTable[] = {\n ";
for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
@@ -246,7 +246,7 @@ void RegisterInfoEmitter::EmitRegUnitPressure(raw_ostream &OS,
OS << RU.Weight << ", ";
}
OS << "};\n"
- << " return RUWeightTable[RegUnit];\n";
+ << " return RUWeightTable[static_cast<unsigned>(RegUnit)];\n";
} else {
OS << " // All register units have unit weight.\n"
<< " return 1;\n";
@@ -330,9 +330,9 @@ void RegisterInfoEmitter::EmitRegUnitPressure(raw_ostream &OS,
<< "register unit.\n"
<< "/// Returns a -1 terminated array of pressure set IDs\n"
<< "const int *" << ClassName << "::\n"
- << "getRegUnitPressureSets(unsigned RegUnit) const {\n"
- << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
- << " && \"invalid register unit\");\n";
+ << "getRegUnitPressureSets(MCRegUnit RegUnit) const {\n"
+ << " assert(static_cast<unsigned>(RegUnit) < "
+ << RegBank.getNumNativeRegUnits() << " && \"invalid register unit\");\n";
OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32)
<< " RUSetStartTable[] = {\n ";
for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
@@ -341,7 +341,8 @@ void RegisterInfoEmitter::EmitRegUnitPressure(raw_ostream &OS,
<< ",";
}
OS << "};\n"
- << " return &RCSetsTable[RUSetStartTable[RegUnit]];\n"
+ << " return "
+ "&RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];\n"
<< "}\n\n";
}
@@ -1168,7 +1169,7 @@ void RegisterInfoEmitter::runTargetHeader(raw_ostream &OS) {
}
OS << " const RegClassWeight &getRegClassWeight("
<< "const TargetRegisterClass *RC) const override;\n"
- << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n"
+ << " unsigned getRegUnitWeight(MCRegUnit RegUnit) const override;\n"
<< " unsigned getNumRegPressureSets() const override;\n"
<< " const char *getRegPressureSetName(unsigned Idx) const override;\n"
<< " unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned "
@@ -1176,7 +1177,7 @@ void RegisterInfoEmitter::runTargetHeader(raw_ostream &OS) {
<< " const int *getRegClassPressureSets("
<< "const TargetRegisterClass *RC) const override;\n"
<< " const int *getRegUnitPressureSets("
- << "unsigned RegUnit) const override;\n"
+ << "MCRegUnit RegUnit) const override;\n"
<< " ArrayRef<const char *> getRegMaskNames() const override;\n"
<< " ArrayRef<const uint32_t *> getRegMasks() const override;\n"
<< " bool isGeneralPurposeRegister(const MachineFunction &, "
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arsenm
approved these changes
Nov 12, 2025
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