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4 changes: 2 additions & 2 deletions llvm/include/llvm/CodeGen/TargetRegisterInfo.h
Original file line number Diff line number Diff line change
Expand Up @@ -958,7 +958,7 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo {
TypeSize getRegSizeInBits(Register Reg, const MachineRegisterInfo &MRI) const;

/// Get the weight in units of pressure for this register unit.
virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
virtual unsigned getRegUnitWeight(MCRegUnit RegUnit) const = 0;

/// Get the number of dimensions of register pressure.
virtual unsigned getNumRegPressureSets() const = 0;
Expand All @@ -978,7 +978,7 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo {

/// Get the dimensions of register pressure impacted by this register unit.
/// Returns a -1 terminated array of pressure set IDs.
virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
virtual const int *getRegUnitPressureSets(MCRegUnit RegUnit) const = 0;

/// Get the scale factor of spill weight for this register class.
virtual float getSpillWeightScaleFactor(const TargetRegisterClass *RC) const;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3781,7 +3781,7 @@ unsigned SIRegisterInfo::getRegPressureSetLimit(const MachineFunction &MF,
llvm_unreachable("Unexpected register pressure set!");
}

const int *SIRegisterInfo::getRegUnitPressureSets(unsigned RegUnit) const {
const int *SIRegisterInfo::getRegUnitPressureSets(MCRegUnit RegUnit) const {
static const int Empty[] = { -1 };

if (RegPressureIgnoredUnits[RegUnit])
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIRegisterInfo.h
Original file line number Diff line number Diff line change
Expand Up @@ -357,7 +357,7 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
const MachineFunction &MF, const VirtRegMap *VRM,
const LiveRegMatrix *Matrix) const override;

const int *getRegUnitPressureSets(unsigned RegUnit) const override;
const int *getRegUnitPressureSets(MCRegUnit RegUnit) const override;

MCRegister getReturnAddressReg(const MachineFunction &MF) const;

Expand Down
4 changes: 2 additions & 2 deletions llvm/unittests/CodeGen/MFCommon.inc
Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,7 @@ public:
static RegClassWeight Bogus{1, 16};
return Bogus;
}
unsigned getRegUnitWeight(unsigned RegUnit) const override { return 1; }
unsigned getRegUnitWeight(MCRegUnit RegUnit) const override { return 1; }
unsigned getNumRegPressureSets() const override { return 0; }
const char *getRegPressureSetName(unsigned Idx) const override {
return "bogus";
Expand All @@ -59,7 +59,7 @@ public:
static const int Bogus[] = {0, -1};
return &Bogus[0];
}
const int *getRegUnitPressureSets(unsigned RegUnit) const override {
const int *getRegUnitPressureSets(MCRegUnit RegUnit) const override {
static const int Bogus[] = {0, -1};
return &Bogus[0];
}
Expand Down
21 changes: 11 additions & 10 deletions llvm/utils/TableGen/RegisterInfoEmitter.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -234,9 +234,9 @@ void RegisterInfoEmitter::EmitRegUnitPressure(raw_ostream &OS,
}
OS << "/// Get the weight in units of pressure for this register unit.\n"
<< "unsigned " << ClassName << "::\n"
<< "getRegUnitWeight(unsigned RegUnit) const {\n"
<< " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
<< " && \"invalid register unit\");\n";
<< "getRegUnitWeight(MCRegUnit RegUnit) const {\n"
<< " assert(static_cast<unsigned>(RegUnit) < "
<< RegBank.getNumNativeRegUnits() << " && \"invalid register unit\");\n";
if (!RegUnitsHaveUnitWeight) {
OS << " static const uint8_t RUWeightTable[] = {\n ";
for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
Expand All @@ -246,7 +246,7 @@ void RegisterInfoEmitter::EmitRegUnitPressure(raw_ostream &OS,
OS << RU.Weight << ", ";
}
OS << "};\n"
<< " return RUWeightTable[RegUnit];\n";
<< " return RUWeightTable[static_cast<unsigned>(RegUnit)];\n";
} else {
OS << " // All register units have unit weight.\n"
<< " return 1;\n";
Expand Down Expand Up @@ -330,9 +330,9 @@ void RegisterInfoEmitter::EmitRegUnitPressure(raw_ostream &OS,
<< "register unit.\n"
<< "/// Returns a -1 terminated array of pressure set IDs\n"
<< "const int *" << ClassName << "::\n"
<< "getRegUnitPressureSets(unsigned RegUnit) const {\n"
<< " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
<< " && \"invalid register unit\");\n";
<< "getRegUnitPressureSets(MCRegUnit RegUnit) const {\n"
<< " assert(static_cast<unsigned>(RegUnit) < "
<< RegBank.getNumNativeRegUnits() << " && \"invalid register unit\");\n";
OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32)
<< " RUSetStartTable[] = {\n ";
for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
Expand All @@ -341,7 +341,8 @@ void RegisterInfoEmitter::EmitRegUnitPressure(raw_ostream &OS,
<< ",";
}
OS << "};\n"
<< " return &RCSetsTable[RUSetStartTable[RegUnit]];\n"
<< " return "
"&RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];\n"
<< "}\n\n";
}

Expand Down Expand Up @@ -1168,15 +1169,15 @@ void RegisterInfoEmitter::runTargetHeader(raw_ostream &OS) {
}
OS << " const RegClassWeight &getRegClassWeight("
<< "const TargetRegisterClass *RC) const override;\n"
<< " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n"
<< " unsigned getRegUnitWeight(MCRegUnit RegUnit) const override;\n"
<< " unsigned getNumRegPressureSets() const override;\n"
<< " const char *getRegPressureSetName(unsigned Idx) const override;\n"
<< " unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned "
"Idx) const override;\n"
<< " const int *getRegClassPressureSets("
<< "const TargetRegisterClass *RC) const override;\n"
<< " const int *getRegUnitPressureSets("
<< "unsigned RegUnit) const override;\n"
<< "MCRegUnit RegUnit) const override;\n"
<< " ArrayRef<const char *> getRegMaskNames() const override;\n"
<< " ArrayRef<const uint32_t *> getRegMasks() const override;\n"
<< " bool isGeneralPurposeRegister(const MachineFunction &, "
Expand Down
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