[AArch64] Remove FEAT_TME assembly and ACLE support #167687
Merged
+5
−314
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
llvmbot
added
clang
Member
|
@llvm/pr-subscribers-lldb @llvm/pr-subscribers-clang-driver Author: Jonathan Thackray (jthackray) ChangesThe Transactional Memory Extension (TME) was introduced as part of Therefore, remove FEAT_TME assembly and ACLE code from llvm, because referenced in Known Issue D24093, documented here: Patch is 21.10 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/167687.diff 21 Files Affected:
diff --git a/clang/include/clang/Basic/BuiltinsAArch64.def b/clang/include/clang/Basic/BuiltinsAArch64.def
index b2aa36acd4506..adb6c941e852a 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.def
+++ b/clang/include/clang/Basic/BuiltinsAArch64.def
@@ -109,12 +109,6 @@ BUILTIN(__builtin_arm_wsrp, "vcC*vC*", "nc")
// Misc
BUILTIN(__builtin_sponentry, "v*", "c")
-// Transactional Memory Extension
-BUILTIN(__builtin_arm_tstart, "WUi", "nj")
-BUILTIN(__builtin_arm_tcommit, "v", "n")
-BUILTIN(__builtin_arm_tcancel, "vWUIi", "n")
-BUILTIN(__builtin_arm_ttest, "WUi", "nc")
-
// Armv8.5-A FP rounding intrinsics
TARGET_BUILTIN(__builtin_arm_rint32zf, "ff", "", "v8.5a")
TARGET_BUILTIN(__builtin_arm_rint32z, "dd", "", "v8.5a")
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index a97e93470987c..d7f36c0f9b79a 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -606,9 +606,6 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
if (HasMTE)
Builder.defineMacro("__ARM_FEATURE_MEMORY_TAGGING", "1");
- if (HasTME)
- Builder.defineMacro("__ARM_FEATURE_TME", "1");
-
if (HasMatMul)
Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
@@ -1173,8 +1170,6 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
}
if (Feature == "+mte")
HasMTE = true;
- if (Feature == "+tme")
- HasTME = true;
if (Feature == "+pauth")
HasPAuth = true;
if (Feature == "+i8mm")
diff --git a/clang/lib/Basic/Targets/AArch64.h b/clang/lib/Basic/Targets/AArch64.h
index 7d0737b2e8df0..1a7aa658e9d87 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -75,7 +75,6 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo {
bool HasDotProd = false;
bool HasFP16FML = false;
bool HasMTE = false;
- bool HasTME = false;
bool HasPAuth = false;
bool HasLS64 = false;
bool HasRandGen = false;
diff --git a/clang/lib/Headers/arm_acle.h b/clang/lib/Headers/arm_acle.h
index fcc2075121b44..97f63e8ecf71f 100644
--- a/clang/lib/Headers/arm_acle.h
+++ b/clang/lib/Headers/arm_acle.h
@@ -821,28 +821,6 @@ __arm_st64bv0(void *__addr, data512_t __value) {
#endif // __ARM_FEATURE_COPROC
-/* 17 Transactional Memory Extension (TME) Intrinsics */
-#if defined(__ARM_FEATURE_TME) && __ARM_FEATURE_TME
-
-#define _TMFAILURE_REASON 0x00007fffu
-#define _TMFAILURE_RTRY 0x00008000u
-#define _TMFAILURE_CNCL 0x00010000u
-#define _TMFAILURE_MEM 0x00020000u
-#define _TMFAILURE_IMP 0x00040000u
-#define _TMFAILURE_ERR 0x00080000u
-#define _TMFAILURE_SIZE 0x00100000u
-#define _TMFAILURE_NEST 0x00200000u
-#define _TMFAILURE_DBG 0x00400000u
-#define _TMFAILURE_INT 0x00800000u
-#define _TMFAILURE_TRIVIAL 0x01000000u
-
-#define __tstart() __builtin_arm_tstart()
-#define __tcommit() __builtin_arm_tcommit()
-#define __tcancel(__arg) __builtin_arm_tcancel(__arg)
-#define __ttest() __builtin_arm_ttest()
-
-#endif /* __ARM_FEATURE_TME */
-
/* 8.7 Armv8.5-A Random number generation intrinsics */
#if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE
static __inline__ int __attribute__((__always_inline__, __nodebug__, target("rand")))
diff --git a/clang/lib/Sema/SemaARM.cpp b/clang/lib/Sema/SemaARM.cpp
index ab37394cd5f98..39f37cc679efa 100644
--- a/clang/lib/Sema/SemaARM.cpp
+++ b/clang/lib/Sema/SemaARM.cpp
@@ -1183,7 +1183,6 @@ bool SemaARM::CheckAArch64BuiltinFunctionCall(const TargetInfo &TI,
l = 0;
u = 15;
break;
- case AArch64::BI__builtin_arm_tcancel: l = 0; u = 65535; break;
}
return SemaRef.BuiltinConstantArgRange(TheCall, i, l, u + l);
diff --git a/clang/test/CodeGen/AArch64/tme.cpp b/clang/test/CodeGen/AArch64/tme.cpp
deleted file mode 100644
index 0e0cfeed7b750..0000000000000
--- a/clang/test/CodeGen/AArch64/tme.cpp
+++ /dev/null
@@ -1,42 +0,0 @@
-// RUN: %clang_cc1 -triple aarch64 -target-feature +tme -emit-llvm %s -o - | FileCheck %s
-// RUN: %clang_cc1 -DUSE_ACLE -triple aarch64 -target-feature +tme -emit-llvm %s -o - | FileCheck %s
-
-#define A -1
-constexpr int f() { return 65536; }
-
-#ifdef USE_ACLE
-#include "arm_acle.h"
-void test_tme_funcs() {
- __tstart();
- (void)__ttest();
- __tcommit();
- __tcancel(0x789a);
- __tcancel(f() + A);
-}
-#else
-void test_tme_funcs() {
- __builtin_arm_tstart();
- (void)__builtin_arm_ttest();
- __builtin_arm_tcommit();
- __builtin_arm_tcancel(0x789a);
- __builtin_arm_tcancel(f() + A);
-}
-#endif
-// CHECK: call i64 @llvm.aarch64.tstart()
-// CHECK: call i64 @llvm.aarch64.ttest()
-// CHECK: call void @llvm.aarch64.tcommit()
-// CHECK: call void @llvm.aarch64.tcancel(i64 30874)
-// CHECK: call void @llvm.aarch64.tcancel(i64 65535)
-
-// CHECK: declare i64 @llvm.aarch64.tstart() #1
-// CHECK: declare i64 @llvm.aarch64.ttest() #1
-// CHECK: declare void @llvm.aarch64.tcommit() #1
-// CHECK: declare void @llvm.aarch64.tcancel(i64 immarg) #1
-
-#ifdef __ARM_FEATURE_TME
-extern "C" void arm_feature_tme_defined() {}
-#endif
-// CHECK: define{{.*}} void @arm_feature_tme_defined()
-
-// CHECK: attributes #1 = { nounwind willreturn }
-
diff --git a/clang/test/Driver/print-supported-extensions-aarch64.c b/clang/test/Driver/print-supported-extensions-aarch64.c
index 7294c33959e7e..5bdb0ead82642 100644
--- a/clang/test/Driver/print-supported-extensions-aarch64.c
+++ b/clang/test/Driver/print-supported-extensions-aarch64.c
@@ -115,5 +115,4 @@
// CHECK-NEXT: the FEAT_THE Enable Armv8.9-A Translation Hardening Extension
// CHECK-NEXT: tlbid FEAT_TLBID Enable Armv9.7-A TLBI Domains extension
// CHECK-NEXT: tlbiw FEAT_TLBIW Enable Armv9.5-A TLBI VMALL for Dirty State
-// CHECK-NEXT: tme FEAT_TME Enable Transactional Memory Extension
// CHECK-NEXT: wfxt FEAT_WFxT Enable Armv8.7-A WFET and WFIT instruction
diff --git a/clang/test/Sema/aarch64-tme-errors.c b/clang/test/Sema/aarch64-tme-errors.c
deleted file mode 100644
index 1cb6f69035141..0000000000000
--- a/clang/test/Sema/aarch64-tme-errors.c
+++ /dev/null
@@ -1,8 +0,0 @@
-// RUN: %clang_cc1 -triple aarch64 -verify %s
-
-#include "arm_acle.h"
-
-void test_no_tme_funcs(void) {
- __tstart(); // expected-error{{call to undeclared function '__tstart'; ISO C99 and later do not support implicit function declarations}}
- __builtin_tstart(); // expected-error{{use of unknown builtin '__builtin_tstart'}}
-}
diff --git a/clang/test/Sema/aarch64-tme-tcancel-errors.c b/clang/test/Sema/aarch64-tme-tcancel-errors.c
deleted file mode 100644
index 365bf81cab2d6..0000000000000
--- a/clang/test/Sema/aarch64-tme-tcancel-errors.c
+++ /dev/null
@@ -1,9 +0,0 @@
-// RUN: %clang_cc1 -triple aarch64 -target-feature +tme -verify %s
-void t_cancel_const(unsigned short u) {
- __builtin_arm_tcancel(u); // expected-error{{argument to '__builtin_arm_tcancel' must be a constant integer}}
-}
-
-// RUN: %clang_cc1 -triple aarch64 -target-feature +tme -verify %s
-void t_cancel_range(void) {
- __builtin_arm_tcancel(0x12345u); // expected-error{{argument value 74565 is outside the valid range [0, 65535]}}
-}
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index c76717fdc990c..130a76f50f719 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -104,6 +104,9 @@ Changes to the AArch64 Backend
* Assembler/disassembler support has been added for Armv9.7-A (2025)
architecture extensions.
+* `FEAT_TME` support has been removed, as it has been withdrawn from
+ all future versions of the A-profile architecture.
+
Changes to the AMDGPU Backend
-----------------------------
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index 4cab6e05ba79f..c84c158c57b8e 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -943,20 +943,7 @@ let TargetPrefix = "aarch64" in {
[IntrWriteMem, IntrArgMemOnly, NoCapture<ArgIndex<0>>, WriteOnly<ArgIndex<0>>]>;
}
-// Transactional Memory Extension (TME) Intrinsics
let TargetPrefix = "aarch64" in {
-def int_aarch64_tstart : ClangBuiltin<"__builtin_arm_tstart">,
- Intrinsic<[llvm_i64_ty], [], [IntrWillReturn]>;
-
-def int_aarch64_tcommit : ClangBuiltin<"__builtin_arm_tcommit">, Intrinsic<[], [], [IntrWillReturn]>;
-
-def int_aarch64_tcancel : ClangBuiltin<"__builtin_arm_tcancel">,
- Intrinsic<[], [llvm_i64_ty], [IntrWillReturn, ImmArg<ArgIndex<0>>]>;
-
-def int_aarch64_ttest : ClangBuiltin<"__builtin_arm_ttest">,
- Intrinsic<[llvm_i64_ty], [],
- [IntrNoMem, IntrHasSideEffects, IntrWillReturn]>;
-
// Armv8.7-A load/store 64-byte intrinsics
defvar data512 = !listsplat(llvm_i64_ty, 8);
def int_aarch64_ld64b: Intrinsic<data512, [llvm_ptr_ty]>;
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index 0e94b78d11d83..374d2ab473643 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -394,9 +394,6 @@ def FeatureTRBE : Extension<"trbe", "TRBE", "FEAT_TRBE",
def FeatureETE : Extension<"ete", "ETE", "FEAT_ETE",
"Enable Embedded Trace Extension", [FeatureTRBE]>;
-def FeatureTME : ExtensionWithMArch<"tme", "TME", "FEAT_TME",
- "Enable Transactional Memory Extension">;
-
//===----------------------------------------------------------------------===//
// Armv9.1 Architecture Extensions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index bb2f083db19ef..0ae03f27cc8e4 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1712,28 +1712,6 @@ class RtSystemI<bit L, dag oops, dag iops, string asm, string operands,
let Inst{4-0} = Rt;
}
-// System instructions for transactional memory extension
-class TMBaseSystemI<bit L, bits<4> CRm, bits<3> op2, dag oops, dag iops,
- string asm, string operands, list<dag> pattern>
- : BaseSystemI<L, oops, iops, asm, operands, pattern>,
- Sched<[WriteSys]> {
- let Inst{20-12} = 0b000110011;
- let Inst{11-8} = CRm;
- let Inst{7-5} = op2;
- let DecoderMethod = "";
-
- let mayLoad = 1;
- let mayStore = 1;
-}
-
-// System instructions for transactional memory - single input operand
-class TMSystemI<bits<4> CRm, string asm, list<dag> pattern>
- : TMBaseSystemI<0b1, CRm, 0b011,
- (outs GPR64:$Rt), (ins), asm, "\t$Rt", pattern> {
- bits<5> Rt;
- let Inst{4-0} = Rt;
-}
-
// System instructions that pass a register argument
// This class assumes the register is for input rather than output.
class RegInputSystemI<bits<4> CRm, bits<3> Op2, string asm,
@@ -1744,23 +1722,6 @@ class RegInputSystemI<bits<4> CRm, bits<3> Op2, string asm,
let Inst{7-5} = Op2;
}
-// System instructions for transactional memory - no operand
-class TMSystemINoOperand<bits<4> CRm, string asm, list<dag> pattern>
- : TMBaseSystemI<0b0, CRm, 0b011, (outs), (ins), asm, "", pattern> {
- let Inst{4-0} = 0b11111;
-}
-
-// System instructions for exit from transactions
-class TMSystemException<bits<3> op1, string asm, list<dag> pattern>
- : I<(outs), (ins timm64_0_65535:$imm), asm, "\t$imm", "", pattern>,
- Sched<[WriteSys]> {
- bits<16> imm;
- let Inst{31-24} = 0b11010100;
- let Inst{23-21} = op1;
- let Inst{20-5} = imm;
- let Inst{4-0} = 0b00000;
-}
-
class APASI : SimpleSystemI<0, (ins GPR64:$Xt), "apas", "\t$Xt">, Sched<[]> {
bits<5> Xt;
let Inst{20-5} = 0b0111001110000000;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index b30e3d06b2c9f..96aeca0fa299a 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -348,8 +348,6 @@ def HasBTI : Predicate<"Subtarget->hasBTI()">,
AssemblerPredicateWithAll<(all_of FeatureBranchTargetId), "bti">;
def HasMTE : Predicate<"Subtarget->hasMTE()">,
AssemblerPredicateWithAll<(all_of FeatureMTE), "mte">;
-def HasTME : Predicate<"Subtarget->hasTME()">,
- AssemblerPredicateWithAll<(all_of FeatureTME), "tme">;
def HasETE : Predicate<"Subtarget->hasETE()">,
AssemblerPredicateWithAll<(all_of FeatureETE), "ete">;
def HasTRBE : Predicate<"Subtarget->hasTRBE()">,
@@ -2488,22 +2486,6 @@ def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
-let Predicates = [HasTME] in {
-
-def TSTART : TMSystemI<0b0000, "tstart",
- [(set GPR64:$Rt, (int_aarch64_tstart))]>;
-
-def TCOMMIT : TMSystemINoOperand<0b0000, "tcommit", [(int_aarch64_tcommit)]>;
-
-def TCANCEL : TMSystemException<0b011, "tcancel",
- [(int_aarch64_tcancel timm64_0_65535:$imm)]>;
-
-def TTEST : TMSystemI<0b0001, "ttest", [(set GPR64:$Rt, (int_aarch64_ttest))]> {
- let mayLoad = 0;
- let mayStore = 0;
-}
-} // HasTME
-
//===----------------------------------------------------------------------===//
// Move immediate instructions.
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index f5dfbdc596510..f60a9e3131d1c 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3847,7 +3847,6 @@ static const struct Extension {
{"rdma", {AArch64::FeatureRDM}},
{"sb", {AArch64::FeatureSB}},
{"ssbs", {AArch64::FeatureSSBS}},
- {"tme", {AArch64::FeatureTME}},
{"fp8", {AArch64::FeatureFP8}},
{"faminmax", {AArch64::FeatureFAMINMAX}},
{"fp8fma", {AArch64::FeatureFP8FMA}},
diff --git a/llvm/test/CodeGen/AArch64/tme.ll b/llvm/test/CodeGen/AArch64/tme.ll
deleted file mode 100644
index d78e8a4de6b59..0000000000000
--- a/llvm/test/CodeGen/AArch64/tme.ll
+++ /dev/null
@@ -1,44 +0,0 @@
-; RUN: llc %s -verify-machineinstrs -o - | FileCheck %s
-
-target triple = "aarch64"
-
-define i64 @test_tstart() #0 {
- %r = tail call i64 @llvm.aarch64.tstart()
- ret i64 %r
-}
-declare i64 @llvm.aarch64.tstart() #1
-; CHECK-LABEL: test_tstart
-; CHECK: tstart x
-
-define i64 @test_ttest() #0 {
- %r = tail call i64 @llvm.aarch64.ttest()
- ret i64 %r
-}
-declare i64 @llvm.aarch64.ttest() #1
-; CHECK-LABEL: test_ttest
-; CHECK: ttest x
-
-define void @test_tcommit() #0 {
- tail call void @llvm.aarch64.tcommit()
- ret void
-}
-declare void @llvm.aarch64.tcommit() #1
-; CHECK-LABEL: test_tcommit
-; CHECK: tcommit
-
-define void @test_tcancel() #0 {
- tail call void @llvm.aarch64.tcancel(i64 0) #1
- tail call void @llvm.aarch64.tcancel(i64 1) #1
- tail call void @llvm.aarch64.tcancel(i64 65534) #1
- tail call void @llvm.aarch64.tcancel(i64 65535) #1
- ret void
-}
-declare void @llvm.aarch64.tcancel(i64 immarg) #1
-; CHECK-LABEL: test_tcancel
-; CHECK: tcancel #0
-; CHECK: tcancel #0x1
-; CHECK: tcancel #0xfffe
-; CHECK: tcancel #0xffff
-
-attributes #0 = { "target-features"="+tme" }
-attributes #1 = { nounwind }
diff --git a/llvm/test/MC/AArch64/directive-arch_extension.s b/llvm/test/MC/AArch64/directive-arch_extension.s
index b8e8696c7abbf..3c754077572a1 100644
--- a/llvm/test/MC/AArch64/directive-arch_extension.s
+++ b/llvm/test/MC/AArch64/directive-arch_extension.s
@@ -186,10 +186,6 @@ sb
msr SSBS, #1
// CHECK: msr SSBS, #1
-.arch_extension tme
-tstart x0
-// CHECK: tstart x0
-
.arch_extension fprcvt
fcvtns s0, d1
// CHECK: fcvtns s0, d1
diff --git a/llvm/test/MC/AArch64/tme-error.s b/llvm/test/MC/AArch64/tme-error.s
deleted file mode 100644
index e498ae68054e1..0000000000000
--- a/llvm/test/MC/AArch64/tme-error.s
+++ /dev/null
@@ -1,47 +0,0 @@
-// Tests for transactional memory extension instructions
-// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+tme < %s 2>&1 | FileCheck %s
-
-tstart
-// CHECK: error: too few operands for instruction
-// CHECK-NEXT: tstart
-tstart x4, x5
-// CHECK: error: invalid operand for instruction
-// CHECK-NEXT: tstart x4, x5
-tstart x4, #1
-// CHECK: error: invalid operand for instruction
-// CHECK-NEXT: tstart x4, #1
-tstart sp
-// CHECK: error: invalid operand for instruction
-// CHECK-NEXT: tstart sp
-
-ttest
-// CHECK: error: too few operands for instruction
-// CHECK-NEXT: ttest
-ttest x4, x5
-// CHECK: error: invalid operand for instruction
-// CHECK-NEXT: ttest x4, x5
-ttest x4, #1
-// CHECK: error: invalid operand for instruction
-// CHECK-NEXT: ttest x4, #1
-ttest sp
-// CHECK: error: invalid operand for instruction
-// CHECK-NEXT: ttest sp
-
-tcommit x4
-// CHECK: error: invalid operand for instruction
-// CHECK-NEXT: tcommit x4
-tcommit sp
-// CHECK: error: invalid operand for instruction
-// CHECK-NEXT: tcommit sp
-
-
-tcancel
-// CHECK: error: too few operands for instruction
-// CHECK-NEXT: tcancel
-tcancel x0
-// CHECK: error: immediate must be an integer in range [0, 65535]
-// CHECK-NEXT: tcancel
-tcancel #65536
-// CHECK: error: immediate must be an integer in range [0, 65535]
-// CHECK-NEXT: tcancel #65536
-
diff --git a/llvm/test/MC/AArch64/tme.s b/llvm/test/MC/AArch64/tme.s
deleted file mode 100644
index cd47274127649..0000000000000
--- a/llvm/test/MC/AArch64/tme.s
+++ /dev/null
@@ -1,24 +0,0 @@
-// Tests for transaction memory extension instructions
-//
-// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+tme < %s | FileCheck %s
-// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-tme < %s 2>&1 | FileCheck %s --check-prefix=NOTME
-
-tstart x3
-ttest x4
-tcommit
-tcancel #0x1234
-
-// CHECK: tstart x3 // encoding: [0x63,0x30,0x23,0xd5]
-// CHECK: ttest x4 // encoding: [0x64,0x31,0x23,0xd5]
-// CHECK: tcommit // encoding: [0x7f,0x30,0x03,0xd5]
-// CHECK: tcancel #0x1234 // encoding: [0x80,0x46,0x62,0xd4]
-
-
-// NOTME: instruction requires: tme
-// NOTME-NEXT: tstart x3
-// NOTME: instruction requires: tme
-// NOTME-NEXT: ttest x4
-// NOTME: instruction requires: tme
-// NOTME-NEXT: tcommit
-// NOTME: instruction requires: tme
-// NOTME-NEXT: tcancel #0x1234
diff --git a/llvm/test/MC/Disassembler/AArch64/tme.txt b/llvm/test/MC/Disassembler/AArch64/tme.txt
deleted file mode 100644
index f250b33e0e1df..0000000000000
--- a/llvm/test/MC/Disassembler/AArch64/tme.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-# Tests for transaction memory extension instructions
-# RUN: llvm-mc -triple=aarch64 -mattr=+tme -disassemble < %s | FileCheck %s
-# RUN: not llvm-mc -triple=aarch64 -mattr=-tme -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOTME
-
-[0x63,0x30,0x23,0xd5]
-[0x64,0x31,0x23,0xd5]
-[0x7f,0x30,0x03,0xd5]
-[0x80,0x46,0x62,0xd4]
-
-# CHECK: tstart x3
-# CHECK: ttest x4
-# CHECK: tcommit
-# CHECK: tcancel #0x1234
-
-# NOTEME: mrs
-# NOTEME-NEXT: mrs
-# NOTEME-NEXT: msr
-# NOTME: warning: invalid instruction encoding
-# NOTME-NEXT: [0x80,0x46,0x62,0xd4]
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 0e5d40ad3c7b1..2e33e51468faf 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1413,7 +1413,6 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_SSBS, AArch64::AEK_SB,
AArch64::AEK_PREDRES, AArch64::AEK_BF16,
AArch64::AEK_I8MM, AArch64::AEK_F32MM,
- AArch64::AEK_F64MM, AArch64::AEK_TME,
AArch64::AEK_LS64, AArch64::AEK_BRBE,
AArch64::AEK_PAUTH, AArch64::AEK_FLAGM,
AArch64::AEK_SME, AArch64::AEK_SMEF64F64,
@@ -1452,7 +1451,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
...
[truncated]
|
Member
|
@llvm/pr-subscribers-clang Author: Jonathan Thackray (jthackray) ChangesThe Transactional Memory Extension (TME) was introduced as part of Therefore, remove FEAT_TME assembly and ACLE code from llvm, because referenced in Known Issue D24093, documented here: Patch is 21.10 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/167687.diff 21 Files Affected:
diff --git a/clang/include/clang/Basic/BuiltinsAArch64.def b/clang/include/clang/Basic/BuiltinsAArch64.def
index b2aa36acd4506..adb6c941e852a 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.def
+++ b/clang/include/clang/Basic/BuiltinsAArch64.def
@@ -109,12 +109,6 @@ BUILTIN(__builtin_arm_wsrp, "vcC*vC*", "nc")
// Misc
BUILTIN(__builtin_sponentry, "v*", "c")
-// Transactional Memory Extension
-BUILTIN(__builtin_arm_tstart, "WUi", "nj")
-BUILTIN(__builtin_arm_tcommit, "v", "n")
-BUILTIN(__builtin_arm_tcancel, "vWUIi", "n")
-BUILTIN(__builtin_arm_ttest, "WUi", "nc")
-
// Armv8.5-A FP rounding intrinsics
TARGET_BUILTIN(__builtin_arm_rint32zf, "ff", "", "v8.5a")
TARGET_BUILTIN(__builtin_arm_rint32z, "dd", "", "v8.5a")
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index a97e93470987c..d7f36c0f9b79a 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -606,9 +606,6 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
if (HasMTE)
Builder.defineMacro("__ARM_FEATURE_MEMORY_TAGGING", "1");
- if (HasTME)
- Builder.defineMacro("__ARM_FEATURE_TME", "1");
-
if (HasMatMul)
Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
@@ -1173,8 +1170,6 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
}
if (Feature == "+mte")
HasMTE = true;
- if (Feature == "+tme")
- HasTME = true;
if (Feature == "+pauth")
HasPAuth = true;
if (Feature == "+i8mm")
diff --git a/clang/lib/Basic/Targets/AArch64.h b/clang/lib/Basic/Targets/AArch64.h
index 7d0737b2e8df0..1a7aa658e9d87 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -75,7 +75,6 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo {
bool HasDotProd = false;
bool HasFP16FML = false;
bool HasMTE = false;
- bool HasTME = false;
bool HasPAuth = false;
bool HasLS64 = false;
bool HasRandGen = false;
diff --git a/clang/lib/Headers/arm_acle.h b/clang/lib/Headers/arm_acle.h
index fcc2075121b44..97f63e8ecf71f 100644
--- a/clang/lib/Headers/arm_acle.h
+++ b/clang/lib/Headers/arm_acle.h
@@ -821,28 +821,6 @@ __arm_st64bv0(void *__addr, data512_t __value) {
#endif // __ARM_FEATURE_COPROC
-/* 17 Transactional Memory Extension (TME) Intrinsics */
-#if defined(__ARM_FEATURE_TME) && __ARM_FEATURE_TME
-
-#define _TMFAILURE_REASON 0x00007fffu
-#define _TMFAILURE_RTRY 0x00008000u
-#define _TMFAILURE_CNCL 0x00010000u
-#define _TMFAILURE_MEM 0x00020000u
-#define _TMFAILURE_IMP 0x00040000u
-#define _TMFAILURE_ERR 0x00080000u
-#define _TMFAILURE_SIZE 0x00100000u
-#define _TMFAILURE_NEST 0x00200000u
-#define _TMFAILURE_DBG 0x00400000u
-#define _TMFAILURE_INT 0x00800000u
-#define _TMFAILURE_TRIVIAL 0x01000000u
-
-#define __tstart() __builtin_arm_tstart()
-#define __tcommit() __builtin_arm_tcommit()
-#define __tcancel(__arg) __builtin_arm_tcancel(__arg)
-#define __ttest() __builtin_arm_ttest()
-
-#endif /* __ARM_FEATURE_TME */
-
/* 8.7 Armv8.5-A Random number generation intrinsics */
#if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE
static __inline__ int __attribute__((__always_inline__, __nodebug__, target("rand")))
diff --git a/clang/lib/Sema/SemaARM.cpp b/clang/lib/Sema/SemaARM.cpp
index ab37394cd5f98..39f37cc679efa 100644
--- a/clang/lib/Sema/SemaARM.cpp
+++ b/clang/lib/Sema/SemaARM.cpp
@@ -1183,7 +1183,6 @@ bool SemaARM::CheckAArch64BuiltinFunctionCall(const TargetInfo &TI,
l = 0;
u = 15;
break;
- case AArch64::BI__builtin_arm_tcancel: l = 0; u = 65535; break;
}
return SemaRef.BuiltinConstantArgRange(TheCall, i, l, u + l);
diff --git a/clang/test/CodeGen/AArch64/tme.cpp b/clang/test/CodeGen/AArch64/tme.cpp
deleted file mode 100644
index 0e0cfeed7b750..0000000000000
--- a/clang/test/CodeGen/AArch64/tme.cpp
+++ /dev/null
@@ -1,42 +0,0 @@
-// RUN: %clang_cc1 -triple aarch64 -target-feature +tme -emit-llvm %s -o - | FileCheck %s
-// RUN: %clang_cc1 -DUSE_ACLE -triple aarch64 -target-feature +tme -emit-llvm %s -o - | FileCheck %s
-
-#define A -1
-constexpr int f() { return 65536; }
-
-#ifdef USE_ACLE
-#include "arm_acle.h"
-void test_tme_funcs() {
- __tstart();
- (void)__ttest();
- __tcommit();
- __tcancel(0x789a);
- __tcancel(f() + A);
-}
-#else
-void test_tme_funcs() {
- __builtin_arm_tstart();
- (void)__builtin_arm_ttest();
- __builtin_arm_tcommit();
- __builtin_arm_tcancel(0x789a);
- __builtin_arm_tcancel(f() + A);
-}
-#endif
-// CHECK: call i64 @llvm.aarch64.tstart()
-// CHECK: call i64 @llvm.aarch64.ttest()
-// CHECK: call void @llvm.aarch64.tcommit()
-// CHECK: call void @llvm.aarch64.tcancel(i64 30874)
-// CHECK: call void @llvm.aarch64.tcancel(i64 65535)
-
-// CHECK: declare i64 @llvm.aarch64.tstart() #1
-// CHECK: declare i64 @llvm.aarch64.ttest() #1
-// CHECK: declare void @llvm.aarch64.tcommit() #1
-// CHECK: declare void @llvm.aarch64.tcancel(i64 immarg) #1
-
-#ifdef __ARM_FEATURE_TME
-extern "C" void arm_feature_tme_defined() {}
-#endif
-// CHECK: define{{.*}} void @arm_feature_tme_defined()
-
-// CHECK: attributes #1 = { nounwind willreturn }
-
diff --git a/clang/test/Driver/print-supported-extensions-aarch64.c b/clang/test/Driver/print-supported-extensions-aarch64.c
index 7294c33959e7e..5bdb0ead82642 100644
--- a/clang/test/Driver/print-supported-extensions-aarch64.c
+++ b/clang/test/Driver/print-supported-extensions-aarch64.c
@@ -115,5 +115,4 @@
// CHECK-NEXT: the FEAT_THE Enable Armv8.9-A Translation Hardening Extension
// CHECK-NEXT: tlbid FEAT_TLBID Enable Armv9.7-A TLBI Domains extension
// CHECK-NEXT: tlbiw FEAT_TLBIW Enable Armv9.5-A TLBI VMALL for Dirty State
-// CHECK-NEXT: tme FEAT_TME Enable Transactional Memory Extension
// CHECK-NEXT: wfxt FEAT_WFxT Enable Armv8.7-A WFET and WFIT instruction
diff --git a/clang/test/Sema/aarch64-tme-errors.c b/clang/test/Sema/aarch64-tme-errors.c
deleted file mode 100644
index 1cb6f69035141..0000000000000
--- a/clang/test/Sema/aarch64-tme-errors.c
+++ /dev/null
@@ -1,8 +0,0 @@
-// RUN: %clang_cc1 -triple aarch64 -verify %s
-
-#include "arm_acle.h"
-
-void test_no_tme_funcs(void) {
- __tstart(); // expected-error{{call to undeclared function '__tstart'; ISO C99 and later do not support implicit function declarations}}
- __builtin_tstart(); // expected-error{{use of unknown builtin '__builtin_tstart'}}
-}
diff --git a/clang/test/Sema/aarch64-tme-tcancel-errors.c b/clang/test/Sema/aarch64-tme-tcancel-errors.c
deleted file mode 100644
index 365bf81cab2d6..0000000000000
--- a/clang/test/Sema/aarch64-tme-tcancel-errors.c
+++ /dev/null
@@ -1,9 +0,0 @@
-// RUN: %clang_cc1 -triple aarch64 -target-feature +tme -verify %s
-void t_cancel_const(unsigned short u) {
- __builtin_arm_tcancel(u); // expected-error{{argument to '__builtin_arm_tcancel' must be a constant integer}}
-}
-
-// RUN: %clang_cc1 -triple aarch64 -target-feature +tme -verify %s
-void t_cancel_range(void) {
- __builtin_arm_tcancel(0x12345u); // expected-error{{argument value 74565 is outside the valid range [0, 65535]}}
-}
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index c76717fdc990c..130a76f50f719 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -104,6 +104,9 @@ Changes to the AArch64 Backend
* Assembler/disassembler support has been added for Armv9.7-A (2025)
architecture extensions.
+* `FEAT_TME` support has been removed, as it has been withdrawn from
+ all future versions of the A-profile architecture.
+
Changes to the AMDGPU Backend
-----------------------------
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index 4cab6e05ba79f..c84c158c57b8e 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -943,20 +943,7 @@ let TargetPrefix = "aarch64" in {
[IntrWriteMem, IntrArgMemOnly, NoCapture<ArgIndex<0>>, WriteOnly<ArgIndex<0>>]>;
}
-// Transactional Memory Extension (TME) Intrinsics
let TargetPrefix = "aarch64" in {
-def int_aarch64_tstart : ClangBuiltin<"__builtin_arm_tstart">,
- Intrinsic<[llvm_i64_ty], [], [IntrWillReturn]>;
-
-def int_aarch64_tcommit : ClangBuiltin<"__builtin_arm_tcommit">, Intrinsic<[], [], [IntrWillReturn]>;
-
-def int_aarch64_tcancel : ClangBuiltin<"__builtin_arm_tcancel">,
- Intrinsic<[], [llvm_i64_ty], [IntrWillReturn, ImmArg<ArgIndex<0>>]>;
-
-def int_aarch64_ttest : ClangBuiltin<"__builtin_arm_ttest">,
- Intrinsic<[llvm_i64_ty], [],
- [IntrNoMem, IntrHasSideEffects, IntrWillReturn]>;
-
// Armv8.7-A load/store 64-byte intrinsics
defvar data512 = !listsplat(llvm_i64_ty, 8);
def int_aarch64_ld64b: Intrinsic<data512, [llvm_ptr_ty]>;
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index 0e94b78d11d83..374d2ab473643 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -394,9 +394,6 @@ def FeatureTRBE : Extension<"trbe", "TRBE", "FEAT_TRBE",
def FeatureETE : Extension<"ete", "ETE", "FEAT_ETE",
"Enable Embedded Trace Extension", [FeatureTRBE]>;
-def FeatureTME : ExtensionWithMArch<"tme", "TME", "FEAT_TME",
- "Enable Transactional Memory Extension">;
-
//===----------------------------------------------------------------------===//
// Armv9.1 Architecture Extensions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index bb2f083db19ef..0ae03f27cc8e4 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1712,28 +1712,6 @@ class RtSystemI<bit L, dag oops, dag iops, string asm, string operands,
let Inst{4-0} = Rt;
}
-// System instructions for transactional memory extension
-class TMBaseSystemI<bit L, bits<4> CRm, bits<3> op2, dag oops, dag iops,
- string asm, string operands, list<dag> pattern>
- : BaseSystemI<L, oops, iops, asm, operands, pattern>,
- Sched<[WriteSys]> {
- let Inst{20-12} = 0b000110011;
- let Inst{11-8} = CRm;
- let Inst{7-5} = op2;
- let DecoderMethod = "";
-
- let mayLoad = 1;
- let mayStore = 1;
-}
-
-// System instructions for transactional memory - single input operand
-class TMSystemI<bits<4> CRm, string asm, list<dag> pattern>
- : TMBaseSystemI<0b1, CRm, 0b011,
- (outs GPR64:$Rt), (ins), asm, "\t$Rt", pattern> {
- bits<5> Rt;
- let Inst{4-0} = Rt;
-}
-
// System instructions that pass a register argument
// This class assumes the register is for input rather than output.
class RegInputSystemI<bits<4> CRm, bits<3> Op2, string asm,
@@ -1744,23 +1722,6 @@ class RegInputSystemI<bits<4> CRm, bits<3> Op2, string asm,
let Inst{7-5} = Op2;
}
-// System instructions for transactional memory - no operand
-class TMSystemINoOperand<bits<4> CRm, string asm, list<dag> pattern>
- : TMBaseSystemI<0b0, CRm, 0b011, (outs), (ins), asm, "", pattern> {
- let Inst{4-0} = 0b11111;
-}
-
-// System instructions for exit from transactions
-class TMSystemException<bits<3> op1, string asm, list<dag> pattern>
- : I<(outs), (ins timm64_0_65535:$imm), asm, "\t$imm", "", pattern>,
- Sched<[WriteSys]> {
- bits<16> imm;
- let Inst{31-24} = 0b11010100;
- let Inst{23-21} = op1;
- let Inst{20-5} = imm;
- let Inst{4-0} = 0b00000;
-}
-
class APASI : SimpleSystemI<0, (ins GPR64:$Xt), "apas", "\t$Xt">, Sched<[]> {
bits<5> Xt;
let Inst{20-5} = 0b0111001110000000;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index b30e3d06b2c9f..96aeca0fa299a 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -348,8 +348,6 @@ def HasBTI : Predicate<"Subtarget->hasBTI()">,
AssemblerPredicateWithAll<(all_of FeatureBranchTargetId), "bti">;
def HasMTE : Predicate<"Subtarget->hasMTE()">,
AssemblerPredicateWithAll<(all_of FeatureMTE), "mte">;
-def HasTME : Predicate<"Subtarget->hasTME()">,
- AssemblerPredicateWithAll<(all_of FeatureTME), "tme">;
def HasETE : Predicate<"Subtarget->hasETE()">,
AssemblerPredicateWithAll<(all_of FeatureETE), "ete">;
def HasTRBE : Predicate<"Subtarget->hasTRBE()">,
@@ -2488,22 +2486,6 @@ def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
-let Predicates = [HasTME] in {
-
-def TSTART : TMSystemI<0b0000, "tstart",
- [(set GPR64:$Rt, (int_aarch64_tstart))]>;
-
-def TCOMMIT : TMSystemINoOperand<0b0000, "tcommit", [(int_aarch64_tcommit)]>;
-
-def TCANCEL : TMSystemException<0b011, "tcancel",
- [(int_aarch64_tcancel timm64_0_65535:$imm)]>;
-
-def TTEST : TMSystemI<0b0001, "ttest", [(set GPR64:$Rt, (int_aarch64_ttest))]> {
- let mayLoad = 0;
- let mayStore = 0;
-}
-} // HasTME
-
//===----------------------------------------------------------------------===//
// Move immediate instructions.
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index f5dfbdc596510..f60a9e3131d1c 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3847,7 +3847,6 @@ static const struct Extension {
{"rdma", {AArch64::FeatureRDM}},
{"sb", {AArch64::FeatureSB}},
{"ssbs", {AArch64::FeatureSSBS}},
- {"tme", {AArch64::FeatureTME}},
{"fp8", {AArch64::FeatureFP8}},
{"faminmax", {AArch64::FeatureFAMINMAX}},
{"fp8fma", {AArch64::FeatureFP8FMA}},
diff --git a/llvm/test/CodeGen/AArch64/tme.ll b/llvm/test/CodeGen/AArch64/tme.ll
deleted file mode 100644
index d78e8a4de6b59..0000000000000
--- a/llvm/test/CodeGen/AArch64/tme.ll
+++ /dev/null
@@ -1,44 +0,0 @@
-; RUN: llc %s -verify-machineinstrs -o - | FileCheck %s
-
-target triple = "aarch64"
-
-define i64 @test_tstart() #0 {
- %r = tail call i64 @llvm.aarch64.tstart()
- ret i64 %r
-}
-declare i64 @llvm.aarch64.tstart() #1
-; CHECK-LABEL: test_tstart
-; CHECK: tstart x
-
-define i64 @test_ttest() #0 {
- %r = tail call i64 @llvm.aarch64.ttest()
- ret i64 %r
-}
-declare i64 @llvm.aarch64.ttest() #1
-; CHECK-LABEL: test_ttest
-; CHECK: ttest x
-
-define void @test_tcommit() #0 {
- tail call void @llvm.aarch64.tcommit()
- ret void
-}
-declare void @llvm.aarch64.tcommit() #1
-; CHECK-LABEL: test_tcommit
-; CHECK: tcommit
-
-define void @test_tcancel() #0 {
- tail call void @llvm.aarch64.tcancel(i64 0) #1
- tail call void @llvm.aarch64.tcancel(i64 1) #1
- tail call void @llvm.aarch64.tcancel(i64 65534) #1
- tail call void @llvm.aarch64.tcancel(i64 65535) #1
- ret void
-}
-declare void @llvm.aarch64.tcancel(i64 immarg) #1
-; CHECK-LABEL: test_tcancel
-; CHECK: tcancel #0
-; CHECK: tcancel #0x1
-; CHECK: tcancel #0xfffe
-; CHECK: tcancel #0xffff
-
-attributes #0 = { "target-features"="+tme" }
-attributes #1 = { nounwind }
diff --git a/llvm/test/MC/AArch64/directive-arch_extension.s b/llvm/test/MC/AArch64/directive-arch_extension.s
index b8e8696c7abbf..3c754077572a1 100644
--- a/llvm/test/MC/AArch64/directive-arch_extension.s
+++ b/llvm/test/MC/AArch64/directive-arch_extension.s
@@ -186,10 +186,6 @@ sb
msr SSBS, #1
// CHECK: msr SSBS, #1
-.arch_extension tme
-tstart x0
-// CHECK: tstart x0
-
.arch_extension fprcvt
fcvtns s0, d1
// CHECK: fcvtns s0, d1
diff --git a/llvm/test/MC/AArch64/tme-error.s b/llvm/test/MC/AArch64/tme-error.s
deleted file mode 100644
index e498ae68054e1..0000000000000
--- a/llvm/test/MC/AArch64/tme-error.s
+++ /dev/null
@@ -1,47 +0,0 @@
-// Tests for transactional memory extension instructions
-// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+tme < %s 2>&1 | FileCheck %s
-
-tstart
-// CHECK: error: too few operands for instruction
-// CHECK-NEXT: tstart
-tstart x4, x5
-// CHECK: error: invalid operand for instruction
-// CHECK-NEXT: tstart x4, x5
-tstart x4, #1
-// CHECK: error: invalid operand for instruction
-// CHECK-NEXT: tstart x4, #1
-tstart sp
-// CHECK: error: invalid operand for instruction
-// CHECK-NEXT: tstart sp
-
-ttest
-// CHECK: error: too few operands for instruction
-// CHECK-NEXT: ttest
-ttest x4, x5
-// CHECK: error: invalid operand for instruction
-// CHECK-NEXT: ttest x4, x5
-ttest x4, #1
-// CHECK: error: invalid operand for instruction
-// CHECK-NEXT: ttest x4, #1
-ttest sp
-// CHECK: error: invalid operand for instruction
-// CHECK-NEXT: ttest sp
-
-tcommit x4
-// CHECK: error: invalid operand for instruction
-// CHECK-NEXT: tcommit x4
-tcommit sp
-// CHECK: error: invalid operand for instruction
-// CHECK-NEXT: tcommit sp
-
-
-tcancel
-// CHECK: error: too few operands for instruction
-// CHECK-NEXT: tcancel
-tcancel x0
-// CHECK: error: immediate must be an integer in range [0, 65535]
-// CHECK-NEXT: tcancel
-tcancel #65536
-// CHECK: error: immediate must be an integer in range [0, 65535]
-// CHECK-NEXT: tcancel #65536
-
diff --git a/llvm/test/MC/AArch64/tme.s b/llvm/test/MC/AArch64/tme.s
deleted file mode 100644
index cd47274127649..0000000000000
--- a/llvm/test/MC/AArch64/tme.s
+++ /dev/null
@@ -1,24 +0,0 @@
-// Tests for transaction memory extension instructions
-//
-// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+tme < %s | FileCheck %s
-// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-tme < %s 2>&1 | FileCheck %s --check-prefix=NOTME
-
-tstart x3
-ttest x4
-tcommit
-tcancel #0x1234
-
-// CHECK: tstart x3 // encoding: [0x63,0x30,0x23,0xd5]
-// CHECK: ttest x4 // encoding: [0x64,0x31,0x23,0xd5]
-// CHECK: tcommit // encoding: [0x7f,0x30,0x03,0xd5]
-// CHECK: tcancel #0x1234 // encoding: [0x80,0x46,0x62,0xd4]
-
-
-// NOTME: instruction requires: tme
-// NOTME-NEXT: tstart x3
-// NOTME: instruction requires: tme
-// NOTME-NEXT: ttest x4
-// NOTME: instruction requires: tme
-// NOTME-NEXT: tcommit
-// NOTME: instruction requires: tme
-// NOTME-NEXT: tcancel #0x1234
diff --git a/llvm/test/MC/Disassembler/AArch64/tme.txt b/llvm/test/MC/Disassembler/AArch64/tme.txt
deleted file mode 100644
index f250b33e0e1df..0000000000000
--- a/llvm/test/MC/Disassembler/AArch64/tme.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-# Tests for transaction memory extension instructions
-# RUN: llvm-mc -triple=aarch64 -mattr=+tme -disassemble < %s | FileCheck %s
-# RUN: not llvm-mc -triple=aarch64 -mattr=-tme -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOTME
-
-[0x63,0x30,0x23,0xd5]
-[0x64,0x31,0x23,0xd5]
-[0x7f,0x30,0x03,0xd5]
-[0x80,0x46,0x62,0xd4]
-
-# CHECK: tstart x3
-# CHECK: ttest x4
-# CHECK: tcommit
-# CHECK: tcancel #0x1234
-
-# NOTEME: mrs
-# NOTEME-NEXT: mrs
-# NOTEME-NEXT: msr
-# NOTME: warning: invalid instruction encoding
-# NOTME-NEXT: [0x80,0x46,0x62,0xd4]
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 0e5d40ad3c7b1..2e33e51468faf 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1413,7 +1413,6 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_SSBS, AArch64::AEK_SB,
AArch64::AEK_PREDRES, AArch64::AEK_BF16,
AArch64::AEK_I8MM, AArch64::AEK_F32MM,
- AArch64::AEK_F64MM, AArch64::AEK_TME,
AArch64::AEK_LS64, AArch64::AEK_BRBE,
AArch64::AEK_PAUTH, AArch64::AEK_FLAGM,
AArch64::AEK_SME, AArch64::AEK_SMEF64F64,
@@ -1452,7 +1451,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
...
[truncated]
|
jthackray
force-pushed
the
users/jthackray/remove_feat_tme
branch
from
8448dd7 to
3397cd7
Compare
jthackray
requested review from
CarolineConcatto,
Lukacma,
amilendra,
kmclaughlin-arm and
rgwott
jthackray
force-pushed
the
users/jthackray/remove_feat_tme
branch
from
3397cd7 to
e3e3392
Compare
DavidSpickett
approved these changes
Nov 13, 2025
Collaborator
DavidSpickett
left a comment
DavidSpickett
left a comment
There was a problem hiding this comment.
Only thing I thought might be here too was the resolver part of the function multi versioning, but I don't see any sign of it in llvm-project or llvm-test-suite so I assume it was never supported.
(compiler-rt/lib/builtins/cpu_model/aarch64/fmv/hwcap.inc for example)
LGTM.
The Transactional Memory Extension (TME) was introduced as part of Armv9-A but has not been adopted by the ecosystem. This mirrors what Arm has observed with similar extensions in other architectures. Therefore, remove FEAT_TME assembly and ACLE code from llvm, because support for TME has now been officially withdrawn, as noted here: ``` FEAT_TME is withdrawn from all future versions of Arm® Architecture Reference Manual for A-profile architecture. ``` referenced in Known Issue D24093, documented here: https://developer.arm.com/documentation/102105/lb-05/
Missed one reference
jthackray
force-pushed
the
users/jthackray/remove_feat_tme
branch
from
e3e3392 to
c534701
Compare
Contributor
Author
|
See also ARM-software/acle#422 which removes this from the ACLE specification. |
Contributor
Author
Thanks, David. Yes, I can't see any sign of TME here either. I've done multiple |
This was referenced Nov 14, 2025
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
The Transactional Memory Extension (TME) was introduced as part of
Armv9-A but has not been adopted by the ecosystem. This mirrors what
Arm has observed with similar extensions in other architectures.
Therefore, remove FEAT_TME assembly and ACLE code from llvm, because
support for TME has now been officially withdrawn, as noted here:
referenced in Known Issue D24093, documented here:
https://developer.arm.com/documentation/102105/lb-05/