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[AArch64] Fix handling of x29/x30 in inline assembly clobbers #167783

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[AArch64] Fix handling of x29/x30 in inline assembly clobbers #167783

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15 changes: 15 additions & 0 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,7 @@
#include "llvm/ADT/SmallVectorExtras.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Analysis/MemoryLocation.h"
Expand Down Expand Up @@ -13157,6 +13158,20 @@ AArch64TargetLowering::getRegForInlineAsmConstraint(
return std::make_pair(unsigned(AArch64::ZT0), &AArch64::ZTRRegClass);
}

// Clang will correctly decode the usage of register name aliases into their
// official names. However, other frontends like `rustc` do not. This allows
// users of these frontends to use the ABI names for registers in LLVM-style
// register constraints.
//
// x31->sp is not included here because it's not a general register and
// needs different handling
unsigned XRegFromAlias = StringSwitch<unsigned>(Constraint.lower())
.Cases({"{x29}", "{fp}"}, AArch64::FP)
.Cases({"{x30}", "{lr}"}, AArch64::LR)
.Default(AArch64::NoRegister);
if (XRegFromAlias != AArch64::NoRegister)
return std::make_pair(XRegFromAlias, &AArch64::GPR64RegClass);

// Use the default implementation in TargetLowering to convert the register
// constraint into a member of a register class.
std::pair<unsigned, const TargetRegisterClass *> Res;
Expand Down
36 changes: 36 additions & 0 deletions llvm/test/CodeGen/AArch64/inline-asm-clobber-x29-x30.ll
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@@ -0,0 +1,36 @@
; RUN: llc -mtriple=aarch64 -verify-machineinstrs < %s | FileCheck %s

; Test that both numeric register names (x29, x30) and their architectural
; aliases (fp, lr) work correctly as clobbers in inline assembly.

define void @clobber_x29() nounwind {
; CHECK-LABEL: clobber_x29:
; CHECK: str x29, [sp
; CHECK: ldr x29, [sp
tail call void asm sideeffect "", "~{x29}"()
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@DavidSpickett DavidSpickett Nov 17, 2025

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I know these are marked tailcall so in theory we should never get load/stores for stack frame management.

However, if you put a nop in the asm statement, you could make this into:
CHECK: str
CHECK-NEXT: nop
CHECK-NEXT: ldr

And it would be bit more robust and immediately clear what the intended behaviour is.

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@DavidSpickett DavidSpickett Nov 17, 2025

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Well, you stated the test intent above (thank you for that too, it often gets forgotten), but it can be visually more clear.

ret void
}

define void @clobber_fp() nounwind {
; CHECK-LABEL: clobber_fp:
; CHECK: str x29, [sp
; CHECK: ldr x29, [sp
tail call void asm sideeffect "", "~{fp}"()
ret void
}

define void @clobber_x30() nounwind {
; CHECK-LABEL: clobber_x30:
; CHECK: str x30, [sp
; CHECK: ldr x30, [sp
tail call void asm sideeffect "", "~{x30}"()
ret void
}

define void @clobber_lr() nounwind {
; CHECK-LABEL: clobber_lr:
; CHECK: str x30, [sp
; CHECK: ldr x30, [sp
tail call void asm sideeffect "", "~{lr}"()
ret void
}
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