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[AArch64][GlobalISel] Don't crash when legalising vector G_SHL #168848

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[AArch64][GlobalISel] Don't crash when legalising vector G_SHL #168848

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8 changes: 4 additions & 4 deletions llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -216,15 +216,15 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.widenScalarToNextPow2(0)
.clampScalar(1, s32, s64)
.clampScalar(0, s32, s64)
.minScalarSameAs(1, 0)
.minScalarEltSameAsIf(isVector(0), 1, 0)
.maxScalarEltSameAsIf(isVector(0), 1, 0)
.clampNumElements(0, v8s8, v16s8)
.clampNumElements(0, v4s16, v8s16)
.clampNumElements(0, v2s32, v4s32)
.clampNumElements(0, v2s64, v2s64)
.moreElementsToNextPow2(0)
.minScalarSameAs(1, 0)
.scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
.minScalarEltSameAsIf(isVector(0), 1, 0)
.maxScalarEltSameAsIf(isVector(0), 1, 0);
.scalarizeIf(scalarOrEltWiderThan(0, 64), 0);
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@arsenm arsenm Nov 20, 2025

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This seems fine but the rules should probably not be so fragile as to crash if you order them wrong

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@cofibrant cofibrant Nov 20, 2025

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Is there a code path where an action can fail with UnableToLegalize but we continue to apply other rules before returning to retry the failing rule after observing a change? If so I can add a check somewhere sensible for a more robust fix.

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@aemerson aemerson Nov 21, 2025

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No, once we hit Unable the whole process will abort.

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@cofibrant cofibrant Nov 21, 2025 •
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Ok, not sure I have a better fix... Basically the action responsible for padding vectors with more undef elements only accepts a single type to expand to, and when applied to binary operations naïvely uses this type for both input operands:

llvm-project/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines 6688 to 6697 in 59ed6df

case TargetOpcode::G_SHL:
case TargetOpcode::G_ASHR:
case TargetOpcode::G_LSHR: {
Observer.changingInstr(MI);
moreElementsVectorSrc(MI, MoreTy, 1);
moreElementsVectorSrc(MI, MoreTy, 2);
moreElementsVectorDst(MI, MoreTy, 0);
Observer.changedInstr(MI);
return Legalized;
}

In other words, it assumes the inputs already agree on their scalar type. One option, I suppose, would be to have this code infer the number of elements from MoreTy, but inherit the scalar element types from each operand for each call to moreElementsVector*(). What do you think?

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@arsenm arsenm Nov 21, 2025

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We probably should have validation that the reported rule makes sense for the given operation as part of the rule parsing. The failure ideally wouldn't be deferred all the way to the application


getActionDefinitionsBuilder(G_PTR_ADD)
.legalFor({{p0, s64}, {v2p0, v2s64}})
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29 changes: 29 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalize-shl-crash.ll
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@@ -0,0 +1,29 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel -o - %s | FileCheck %s

target triple = "aarch64-unknown-unknown"

; Check we don't crash here.

define <2 x i8> @test() {
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@arsenm arsenm Nov 20, 2025

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Can you add this case to one of the existing shl tests

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@cofibrant cofibrant Nov 20, 2025

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Will do! Thanks!

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@cofibrant cofibrant Nov 21, 2025 •
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I couldn't find another IR test for legalising shifts. I found https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir, though. Should I add the MIR here?

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@arsenm arsenm Nov 21, 2025

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test/CodeGen/AArch64/shift.ll seems to have a -global-isel run line?

; CHECK-LABEL: test:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: mov w9, #0 // =0x0
; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: fmov s1, w9
; CHECK-NEXT: mov v0.b[1], w8
; CHECK-NEXT: mov v1.b[1], w9
; CHECK-NEXT: ushl v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umov w8, v0.b[0]
; CHECK-NEXT: umov w9, v0.b[1]
; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: mov v0.s[1], w9
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
entry:
%zeroes = zext <2 x i1> zeroinitializer to <2 x i32>
%ones = shl <2 x i32> splat (i32 1), %zeroes
%ones.trunc = trunc <2 x i32> %ones to <2 x i8>
ret <2 x i8> %ones.trunc
}