[X86][NFC] Add `-show-mc-encoding` to check register misuse #169264

phoebewang · 2025-11-24T01:56:32Z

No description provided.

llvmbot · 2025-11-24T01:57:06Z

@llvm/pr-subscribers-backend-x86

Author: Phoebe Wang (phoebewang)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/169264.diff

4 Files Affected:

(modified) llvm/test/CodeGen/X86/apx/no-rex2-general.ll (+35-35)
(modified) llvm/test/CodeGen/X86/apx/no-rex2-pseudo-amx.ll (+8-8)
(modified) llvm/test/CodeGen/X86/apx/no-rex2-pseudo-x87.ll (+11-11)
(modified) llvm/test/CodeGen/X86/apx/no-rex2-special.ll (+37-37)

diff --git a/llvm/test/CodeGen/X86/apx/no-rex2-general.ll b/llvm/test/CodeGen/X86/apx/no-rex2-general.ll
index 2b34739fa80e3..6f31aef9aee98 100644
--- a/llvm/test/CodeGen/X86/apx/no-rex2-general.ll
+++ b/llvm/test/CodeGen/X86/apx/no-rex2-general.ll
@@ -1,17 +1,17 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,+ssse3,+egpr  | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,+ssse3,+egpr,+avx | FileCheck %s --check-prefixes=CHECK,AVX
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,+ssse3,+egpr --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,+ssse3,+egpr,+avx --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,AVX
 
 define i32 @map0(ptr nocapture noundef readonly %a, i64 noundef %b) {
 ; CHECK-LABEL: map0:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movq %rsi, %r16
-; CHECK-NEXT:    movq %rdi, %r17
+; CHECK-NEXT:    movq %rsi, %r16 # encoding: [0xd5,0x18,0x89,0xf0]
+; CHECK-NEXT:    movq %rdi, %r17 # encoding: [0xd5,0x18,0x89,0xf9]
 ; CHECK-NEXT:    #APP
-; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop # encoding: [0x90]
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movl (%r17,%r16,4), %eax
-; CHECK-NEXT:    retq
+; CHECK-NEXT:    movl (%r17,%r16,4), %eax # encoding: [0xd5,0x30,0x8b,0x04,0x81]
+; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %add.ptr = getelementptr inbounds i32, ptr %a, i64 %b
   tail call void asm sideeffect "nop", "~{eax},~{ecx},~{edx},~{esi},~{edi},~{r8},~{r9},~{r10},~{r11}"()
@@ -22,23 +22,23 @@ entry:
 define i32 @map1_or_vex(<2 x double> noundef %a) nounwind {
 ; SSE-LABEL: map1_or_vex:
 ; SSE:       # %bb.0: # %entry
-; SSE-NEXT:    cvtsd2si %xmm0, %r16d
+; SSE-NEXT:    cvtsd2si %xmm0, %r16d # encoding: [0xf2,0xd5,0xc0,0x2d,0xc0]
 ; SSE-NEXT:    #APP
-; SSE-NEXT:    nop
+; SSE-NEXT:    nop # encoding: [0x90]
 ; SSE-NEXT:    #NO_APP
-; SSE-NEXT:    movl %r16d, %eax
-; SSE-NEXT:    retq
+; SSE-NEXT:    movl %r16d, %eax # encoding: [0xd5,0x40,0x89,0xc0]
+; SSE-NEXT:    retq # encoding: [0xc3]
 ;
 ; AVX-LABEL: map1_or_vex:
 ; AVX:       # %bb.0: # %entry
-; AVX-NEXT:    pushq %rbx
-; AVX-NEXT:    vcvtsd2si %xmm0, %ebx
+; AVX-NEXT:    pushq %rbx # encoding: [0x53]
+; AVX-NEXT:    vcvtsd2si %xmm0, %ebx # encoding: [0xc5,0xfb,0x2d,0xd8]
 ; AVX-NEXT:    #APP
-; AVX-NEXT:    nop
+; AVX-NEXT:    nop # encoding: [0x90]
 ; AVX-NEXT:    #NO_APP
-; AVX-NEXT:    movl %ebx, %eax
-; AVX-NEXT:    popq %rbx
-; AVX-NEXT:    retq
+; AVX-NEXT:    movl %ebx, %eax # encoding: [0x89,0xd8]
+; AVX-NEXT:    popq %rbx # encoding: [0x5b]
+; AVX-NEXT:    retq # encoding: [0xc3]
 entry:
   %0 = tail call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %a)
   tail call void asm sideeffect "nop", "~{eax},~{ecx},~{edx},~{esi},~{edi},~{r8},~{r9},~{r10},~{r11}"()
@@ -48,31 +48,31 @@ entry:
 define <2 x i64> @map2_or_vex(ptr nocapture noundef readonly %b, i64 noundef %c) nounwind {
 ; SSE-LABEL: map2_or_vex:
 ; SSE:       # %bb.0: # %entry
-; SSE-NEXT:    pushq %r14
-; SSE-NEXT:    pushq %rbx
-; SSE-NEXT:    movq %rsi, %rbx
-; SSE-NEXT:    movq %rdi, %r14
+; SSE-NEXT:    pushq %r14 # encoding: [0x41,0x56]
+; SSE-NEXT:    pushq %rbx # encoding: [0x53]
+; SSE-NEXT:    movq %rsi, %rbx # encoding: [0x48,0x89,0xf3]
+; SSE-NEXT:    movq %rdi, %r14 # encoding: [0x49,0x89,0xfe]
 ; SSE-NEXT:    #APP
-; SSE-NEXT:    nop
+; SSE-NEXT:    nop # encoding: [0x90]
 ; SSE-NEXT:    #NO_APP
-; SSE-NEXT:    pabsb (%r14,%rbx,4), %xmm0
-; SSE-NEXT:    popq %rbx
-; SSE-NEXT:    popq %r14
-; SSE-NEXT:    retq
+; SSE-NEXT:    pabsb (%r14,%rbx,4), %xmm0 # encoding: [0x66,0x41,0x0f,0x38,0x1c,0x04,0x9e]
+; SSE-NEXT:    popq %rbx # encoding: [0x5b]
+; SSE-NEXT:    popq %r14 # encoding: [0x41,0x5e]
+; SSE-NEXT:    retq # encoding: [0xc3]
 ;
 ; AVX-LABEL: map2_or_vex:
 ; AVX:       # %bb.0: # %entry
-; AVX-NEXT:    pushq %r14
-; AVX-NEXT:    pushq %rbx
-; AVX-NEXT:    movq %rsi, %rbx
-; AVX-NEXT:    movq %rdi, %r14
+; AVX-NEXT:    pushq %r14 # encoding: [0x41,0x56]
+; AVX-NEXT:    pushq %rbx # encoding: [0x53]
+; AVX-NEXT:    movq %rsi, %rbx # encoding: [0x48,0x89,0xf3]
+; AVX-NEXT:    movq %rdi, %r14 # encoding: [0x49,0x89,0xfe]
 ; AVX-NEXT:    #APP
-; AVX-NEXT:    nop
+; AVX-NEXT:    nop # encoding: [0x90]
 ; AVX-NEXT:    #NO_APP
-; AVX-NEXT:    vpabsb (%r14,%rbx,4), %xmm0
-; AVX-NEXT:    popq %rbx
-; AVX-NEXT:    popq %r14
-; AVX-NEXT:    retq
+; AVX-NEXT:    vpabsb (%r14,%rbx,4), %xmm0 # encoding: [0xc4,0xc2,0x79,0x1c,0x04,0x9e]
+; AVX-NEXT:    popq %rbx # encoding: [0x5b]
+; AVX-NEXT:    popq %r14 # encoding: [0x41,0x5e]
+; AVX-NEXT:    retq # encoding: [0xc3]
 entry:
   tail call void asm sideeffect "nop", "~{eax},~{ecx},~{edx},~{esi},~{edi},~{r8},~{r9},~{r10},~{r11}"()
   %add.ptr = getelementptr inbounds i32, ptr %b, i64 %c
diff --git a/llvm/test/CodeGen/X86/apx/no-rex2-pseudo-amx.ll b/llvm/test/CodeGen/X86/apx/no-rex2-pseudo-amx.ll
index c193680607f76..a6ab98f8bf03e 100644
--- a/llvm/test/CodeGen/X86/apx/no-rex2-pseudo-amx.ll
+++ b/llvm/test/CodeGen/X86/apx/no-rex2-pseudo-amx.ll
@@ -1,18 +1,18 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+amx-tile,+egpr | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+amx-tile,+egpr --show-mc-encoding | FileCheck %s
 
 define dso_local void @amx(ptr noundef %data) nounwind {
 ; CHECK-LABEL: amx:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    pushq %rbx
-; CHECK-NEXT:    movq %rdi, %rbx
+; CHECK-NEXT:    pushq %rbx # encoding: [0x53]
+; CHECK-NEXT:    movq %rdi, %rbx # encoding: [0x48,0x89,0xfb]
 ; CHECK-NEXT:    #APP
-; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop # encoding: [0x90]
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movl $8, %eax
-; CHECK-NEXT:    tileloadd (%rbx,%rax), %tmm4
-; CHECK-NEXT:    popq %rbx
-; CHECK-NEXT:    retq
+; CHECK-NEXT:    movl $8, %eax # encoding: [0xb8,0x08,0x00,0x00,0x00]
+; CHECK-NEXT:    tileloadd (%rbx,%rax), %tmm4 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7b,0x4b,0x24,0x03]
+; CHECK-NEXT:    popq %rbx # encoding: [0x5b]
+; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   tail call void asm sideeffect "nop", "~{eax},~{ecx},~{edx},~{esi},~{edi},~{r8},~{r9},~{r10},~{r11}"()
   call void @llvm.x86.tileloadd64(i8 4, ptr %data, i64 8)
diff --git a/llvm/test/CodeGen/X86/apx/no-rex2-pseudo-x87.ll b/llvm/test/CodeGen/X86/apx/no-rex2-pseudo-x87.ll
index 4692a58d095a6..e7bc0c362cad3 100644
--- a/llvm/test/CodeGen/X86/apx/no-rex2-pseudo-x87.ll
+++ b/llvm/test/CodeGen/X86/apx/no-rex2-pseudo-x87.ll
@@ -1,21 +1,21 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=-sse,+egpr | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=-sse,+egpr --show-mc-encoding | FileCheck %s
 
 define void @x87(ptr %0, ptr %1) nounwind {
 ; CHECK-LABEL: x87:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %r14
-; CHECK-NEXT:    pushq %rbx
-; CHECK-NEXT:    movq %rsi, %rbx
-; CHECK-NEXT:    movq %rdi, %r14
+; CHECK-NEXT:    pushq %r14 # encoding: [0x41,0x56]
+; CHECK-NEXT:    pushq %rbx # encoding: [0x53]
+; CHECK-NEXT:    movq %rsi, %rbx # encoding: [0x48,0x89,0xf3]
+; CHECK-NEXT:    movq %rdi, %r14 # encoding: [0x49,0x89,0xfe]
 ; CHECK-NEXT:    #APP
-; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop # encoding: [0x90]
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    flds (%r14)
-; CHECK-NEXT:    fstps (%rbx)
-; CHECK-NEXT:    popq %rbx
-; CHECK-NEXT:    popq %r14
-; CHECK-NEXT:    retq
+; CHECK-NEXT:    flds (%r14) # encoding: [0x41,0xd9,0x06]
+; CHECK-NEXT:    fstps (%rbx) # encoding: [0xd9,0x1b]
+; CHECK-NEXT:    popq %rbx # encoding: [0x5b]
+; CHECK-NEXT:    popq %r14 # encoding: [0x41,0x5e]
+; CHECK-NEXT:    retq # encoding: [0xc3]
   tail call void asm sideeffect "nop", "~{eax},~{ecx},~{edx},~{esi},~{edi},~{r8},~{r9},~{r10},~{r11}"()
   %3 = load float, ptr %0
   store float %3, ptr %1
diff --git a/llvm/test/CodeGen/X86/apx/no-rex2-special.ll b/llvm/test/CodeGen/X86/apx/no-rex2-special.ll
index f2025b5c8cbf8..9b89bce283b15 100644
--- a/llvm/test/CodeGen/X86/apx/no-rex2-special.ll
+++ b/llvm/test/CodeGen/X86/apx/no-rex2-special.ll
@@ -1,20 +1,20 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+xsave,+egpr  | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+xsave,+egpr --show-mc-encoding | FileCheck %s
 
 define void @test_xsave(ptr %ptr, i32 %hi, i32 %lo) nounwind {
 ; CHECK-LABEL: test_xsave:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %rbx
-; CHECK-NEXT:    movl %edx, %r16d
-; CHECK-NEXT:    movl %esi, %edx
-; CHECK-NEXT:    movq %rdi, %rbx
+; CHECK-NEXT:    pushq %rbx # encoding: [0x53]
+; CHECK-NEXT:    movl %edx, %r16d # encoding: [0xd5,0x10,0x89,0xd0]
+; CHECK-NEXT:    movl %esi, %edx # encoding: [0x89,0xf2]
+; CHECK-NEXT:    movq %rdi, %rbx # encoding: [0x48,0x89,0xfb]
 ; CHECK-NEXT:    #APP
-; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop # encoding: [0x90]
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movl %r16d, %eax
-; CHECK-NEXT:    xsave (%rbx)
-; CHECK-NEXT:    popq %rbx
-; CHECK-NEXT:    retq
+; CHECK-NEXT:    movl %r16d, %eax # encoding: [0xd5,0x40,0x89,0xc0]
+; CHECK-NEXT:    xsave (%rbx) # encoding: [0x0f,0xae,0x23]
+; CHECK-NEXT:    popq %rbx # encoding: [0x5b]
+; CHECK-NEXT:    retq # encoding: [0xc3]
   tail call void asm sideeffect "nop", "~{eax},~{ecx},~{esi},~{edi},~{r8},~{r9},~{r10},~{r11}"()
   call void @llvm.x86.xsave(ptr %ptr, i32 %hi, i32 %lo)
   ret void;
@@ -24,17 +24,17 @@ declare void @llvm.x86.xsave(ptr, i32, i32)
 define void @test_xsave64(ptr %ptr, i32 %hi, i32 %lo) nounwind {
 ; CHECK-LABEL: test_xsave64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %rbx
-; CHECK-NEXT:    movl %edx, %r16d
-; CHECK-NEXT:    movl %esi, %edx
-; CHECK-NEXT:    movq %rdi, %rbx
+; CHECK-NEXT:    pushq %rbx # encoding: [0x53]
+; CHECK-NEXT:    movl %edx, %r16d # encoding: [0xd5,0x10,0x89,0xd0]
+; CHECK-NEXT:    movl %esi, %edx # encoding: [0x89,0xf2]
+; CHECK-NEXT:    movq %rdi, %rbx # encoding: [0x48,0x89,0xfb]
 ; CHECK-NEXT:    #APP
-; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop # encoding: [0x90]
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movl %r16d, %eax
-; CHECK-NEXT:    xsave64 (%rbx)
-; CHECK-NEXT:    popq %rbx
-; CHECK-NEXT:    retq
+; CHECK-NEXT:    movl %r16d, %eax # encoding: [0xd5,0x40,0x89,0xc0]
+; CHECK-NEXT:    xsave64 (%rbx) # encoding: [0x48,0x0f,0xae,0x23]
+; CHECK-NEXT:    popq %rbx # encoding: [0x5b]
+; CHECK-NEXT:    retq # encoding: [0xc3]
   tail call void asm sideeffect "nop", "~{eax},~{ecx},~{esi},~{edi},~{r8},~{r9},~{r10},~{r11}"()
   call void @llvm.x86.xsave64(ptr %ptr, i32 %hi, i32 %lo)
   ret void;
@@ -44,17 +44,17 @@ declare void @llvm.x86.xsave64(ptr, i32, i32)
 define void @test_xrstor(ptr %ptr, i32 %hi, i32 %lo) nounwind {
 ; CHECK-LABEL: test_xrstor:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %rbx
-; CHECK-NEXT:    movl %edx, %r16d
-; CHECK-NEXT:    movl %esi, %edx
-; CHECK-NEXT:    movq %rdi, %rbx
+; CHECK-NEXT:    pushq %rbx # encoding: [0x53]
+; CHECK-NEXT:    movl %edx, %r16d # encoding: [0xd5,0x10,0x89,0xd0]
+; CHECK-NEXT:    movl %esi, %edx # encoding: [0x89,0xf2]
+; CHECK-NEXT:    movq %rdi, %rbx # encoding: [0x48,0x89,0xfb]
 ; CHECK-NEXT:    #APP
-; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop # encoding: [0x90]
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movl %r16d, %eax
-; CHECK-NEXT:    xrstor (%rbx)
-; CHECK-NEXT:    popq %rbx
-; CHECK-NEXT:    retq
+; CHECK-NEXT:    movl %r16d, %eax # encoding: [0xd5,0x40,0x89,0xc0]
+; CHECK-NEXT:    xrstor (%rbx) # encoding: [0x0f,0xae,0x2b]
+; CHECK-NEXT:    popq %rbx # encoding: [0x5b]
+; CHECK-NEXT:    retq # encoding: [0xc3]
   tail call void asm sideeffect "nop", "~{eax},~{ecx},~{esi},~{edi},~{r8},~{r9},~{r10},~{r11}"()
   call void @llvm.x86.xrstor(ptr %ptr, i32 %hi, i32 %lo)
   ret void;
@@ -64,17 +64,17 @@ declare void @llvm.x86.xrstor(ptr, i32, i32)
 define void @test_xrstor64(ptr %ptr, i32 %hi, i32 %lo) nounwind {
 ; CHECK-LABEL: test_xrstor64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushq %rbx
-; CHECK-NEXT:    movl %edx, %r16d
-; CHECK-NEXT:    movl %esi, %edx
-; CHECK-NEXT:    movq %rdi, %rbx
+; CHECK-NEXT:    pushq %rbx # encoding: [0x53]
+; CHECK-NEXT:    movl %edx, %r16d # encoding: [0xd5,0x10,0x89,0xd0]
+; CHECK-NEXT:    movl %esi, %edx # encoding: [0x89,0xf2]
+; CHECK-NEXT:    movq %rdi, %rbx # encoding: [0x48,0x89,0xfb]
 ; CHECK-NEXT:    #APP
-; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop # encoding: [0x90]
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movl %r16d, %eax
-; CHECK-NEXT:    xrstor64 (%rbx)
-; CHECK-NEXT:    popq %rbx
-; CHECK-NEXT:    retq
+; CHECK-NEXT:    movl %r16d, %eax # encoding: [0xd5,0x40,0x89,0xc0]
+; CHECK-NEXT:    xrstor64 (%rbx) # encoding: [0x48,0x0f,0xae,0x2b]
+; CHECK-NEXT:    popq %rbx # encoding: [0x5b]
+; CHECK-NEXT:    retq # encoding: [0xc3]
   tail call void asm sideeffect "nop", "~{eax},~{ecx},~{esi},~{edi},~{r8},~{r9},~{r10},~{r11}"()
   call void @llvm.x86.xrstor64(ptr %ptr, i32 %hi, i32 %lo)
   ret void;

llvm-ci · 2025-11-24T13:42:27Z

LLVM Buildbot has detected a new failure on builder llvm-nvptx-nvidia-win running on as-builder-8 while building llvm at step 7 "test-build-unified-tree-check-llvm".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/54/builds/14979

Here is the relevant piece of the build log for the reference

Step 7 (test-build-unified-tree-check-llvm) failure: test (failure)
******************** TEST 'LLVM-Unit :: Support/./SupportTests.exe/79/105' FAILED ********************
Script(shard):
--
GTEST_OUTPUT=json:C:\buildbot\as-builder-8\llvm-nvptx-nvidia-win\build\unittests\Support\.\SupportTests.exe-LLVM-Unit-16956-79-105.json GTEST_SHUFFLE=0 GTEST_TOTAL_SHARDS=105 GTEST_SHARD_INDEX=79 C:\buildbot\as-builder-8\llvm-nvptx-nvidia-win\build\unittests\Support\.\SupportTests.exe
--


Note: This is test shard 80 of 105.

[==========] Running 16 tests from 16 test suites.

[----------] Global test environment set-up.

[----------] 1 test from BinaryStreamTest

[ RUN      ] BinaryStreamTest.DropOperations

[       OK ] BinaryStreamTest.DropOperations (0 ms)

[----------] 1 test from BinaryStreamTest (0 ms total)



[----------] 1 test from CommandLineTest

[ RUN      ] CommandLineTest.TokenizeAndMarkEOLs

[       OK ] CommandLineTest.TokenizeAndMarkEOLs (0 ms)

[----------] 1 test from CommandLineTest (0 ms total)



[----------] 1 test from DataExtractorTest

[ RUN      ] DataExtractorTest.LEB128_error

[       OK ] DataExtractorTest.LEB128_error (0 ms)

[----------] 1 test from DataExtractorTest (0 ms total)



[----------] 1 test from Error

[ RUN      ] Error.ForwardToExpected

[       OK ] Error.ForwardToExpected (0 ms)

[----------] 1 test from Error (0 ms total)
...

)

[X86][NFC] Add -show-mc-encoding to check register misuse

c41a2f8

phoebewang requested a review from KanRobert November 24, 2025 01:56

llvmbot added the backend:X86 label Nov 24, 2025

phoebewang mentioned this pull request Nov 24, 2025

X86: Stop overriding getRegClass #155128

Open

KanRobert approved these changes Nov 24, 2025

View reviewed changes

phoebewang merged commit a27842c into llvm:main Nov 24, 2025
11 of 12 checks passed

phoebewang deleted the NFC branch November 24, 2025 13:16

aadeshps-mcw pushed a commit to aadeshps-mcw/llvm-project that referenced this pull request Nov 26, 2025

[X86][NFC] Add -show-mc-encoding to check register misuse (llvm#169264

6dfa40e

)

Priyanshu3820 pushed a commit to Priyanshu3820/llvm-project that referenced this pull request Nov 26, 2025

[X86][NFC] Add -show-mc-encoding to check register misuse (llvm#169264

d433b95

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[X86][NFC] Add -show-mc-encoding to check register misuse #169264

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[X86][NFC] Add `-show-mc-encoding` to check register misuse #169264

[X86][NFC] Add `-show-mc-encoding` to check register misuse #169264