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[AArch64] Fix metrics of ASIMD instructions in Neoverse N3 #169790

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Merged
merged 7 commits into from
Nov 28, 2025
Merged

[AArch64] Fix metrics of ASIMD instructions in Neoverse N3 #169790

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effe312
[AArch64] Fix scalar instructions in Neoverse N3
Nov 26, 2025
68fce05
Add character class
Nov 27, 2025
f93f671
[AArch64] Fix scalar instructions in Neoverse N3
Nov 26, 2025
632732a
Add character class
Nov 27, 2025
09344e9
Merge branch 'main' into scalars
Asher8118 Nov 28, 2025
05fabad
Merge branch 'scalars' of https://github.com/Rin18/llvm-project-fork …
Nov 28, 2025
1206933
Fix test
Nov 28, 2025
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38 changes: 19 additions & 19 deletions llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1097,7 +1097,7 @@ def : SchedAlias<WriteVq, N3Write_2c_1V>;
// ASIMD shift accumulate
def : InstRW<[N3Wr_ADA, N3Rd_ADA], (instregex "^[SU]ABAL?v",
"^[SU]ADALPv",
"^[SU]R?SRAv")>;
"^[SU]R?SRA(v|d)")>;

// ASIMD arith, reduce, 4H/4S
def : InstRW<[N3Write_3c_1V1], (instregex "^[SU]?ADDL?Vv4i(16|32)v$")>;
Expand Down Expand Up @@ -1138,30 +1138,30 @@ def : InstRW<[N3Wr_VMAH, N3Rd_VMAH], (instregex "^SQRDMLAHv", "^SQRDMLSHv")>;
def : InstRW<[N3Wr_VMAL, N3Rd_VMAL], (instregex "^[SU]MLALv", "^[SU]MLSLv")>;

// ASIMD multiply accumulate saturating long
def : InstRW<[N3Wr_VMASL, N3Rd_VMASL], (instregex "^SQDMLALv", "^SQDMLSLv")>;
def : InstRW<[N3Wr_VMASL, N3Rd_VMASL], (instregex "^SQDMLAL(v|i16|i32)", "^SQDMLSL(v|i16|i32)")>;

// ASIMD multiply/multiply long (8x8) polynomial, D-form
// ASIMD multiply/multiply long (8x8) polynomial, Q-form
def : InstRW<[N3Write_2c_1V0], (instregex "^PMULL?(v8i8|v16i8)$")>;

// ASIMD multiply long
def : InstRW<[N3Write_4c_1V0], (instregex "^[SU]MULLv", "^SQDMULLv")>;
def : InstRW<[N3Write_4c_1V0], (instregex "^[SU]MULLv", "^SQDMULL(v|i16|i32)")>;

// ASIMD shift by immed, basic
def : InstRW<[N3Write_2c_1V1], (instregex "^SHLv", "^SHLLv", "^SHRNv",
"^SSHLLv", "^SSHRv", "^USHLLv",
"^USHRv")>;
def : InstRW<[N3Write_2c_1V1], (instregex "^SHL(v|d)", "^SHLLv", "^SHRNv",
"^SSHLLv", "^SSHR(v|d)", "^USHLLv",
"^USHR(v|d)")>;

// ASIMD shift by immed and insert, basic
def : InstRW<[N3Write_2c_1V1], (instregex "^SLIv", "^SRIv")>;
def : InstRW<[N3Write_2c_1V1], (instregex "^SLI(v|d)", "^SRI(v|d)")>;

// ASIMD shift by immed, complex
def : InstRW<[N3Write_4c_1V1],
(instregex "^RSHRNv", "^SQRSHRNv", "^SQRSHRUNv",
(instregex "^RSHRNv", "^SQRSHRN[vbhs]", "^SQRSHRUN[vbhs]",
"^(SQSHLU?|UQSHL)[bhsd]$",
"^(SQSHLU?|UQSHL)(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)_shift$",
"^SQSHRNv", "^SQSHRUNv", "^SRSHRv", "^UQRSHRNv",
"^UQSHRNv", "^URSHRv")>;
"^SQSHRN[vbhs]", "^SQSHRUN[vbhs]", "^SRSHR(v|d)",
"^UQRSHRN[vbhs]", "^UQSHRN[vbhs]","^URSHR(v|d)")>;

// ASIMD shift by register, basic
def : InstRW<[N3Write_2c_1V1], (instregex "^[SU]SHLv")>;
Expand Down Expand Up @@ -1197,16 +1197,16 @@ def : InstRW<[N3Write_3c_1V0], (instregex "^FCVTL(v2|v4)i32")>;
def : InstRW<[N3Write_4c_2V0], (instregex "^FCVTN(v4|v8)i16")>;

// ASIMD FP convert, narrow (F64 to F32)
def : InstRW<[N3Write_3c_1V0], (instregex "^FCVTN(v2|v4)i32",
def : InstRW<[N3Write_3c_1V0], (instregex "^FCVTN(v2|v4)i32", "^FCVTXNv1i64",
"^FCVTXN(v2|v4)f32")>;

// ASIMD FP convert, other, D-form F32 and Q-form F64
def : InstRW<[N3Write_3c_1V0], (instregex "^[FSU]CVT[AMNPZ][SU]v2f(32|64)$",
"^[SU]CVTFv2f(32|64)$")>;
def : InstRW<[N3Write_3c_1V0], (instregex "^[FSU]CVT[AMNPZ][SU](v2f(32|64)|s|d|v1i32|v1i64|v2i32_shift|v2i64_shift)$",
"^[SU]CVTF(v2f(32|64)|s|d|v1i32|v1i64|v2i32_shift|v2i64_shift)$")>;

// ASIMD FP convert, other, D-form F16 and Q-form F32
def : InstRW<[N3Write_4c_2V0], (instregex "^[FSU]CVT[AMNPZ][SU]v4f(16|32)$",
"^[SU]CVTFv4f(16|32)$")>;
def : InstRW<[N3Write_4c_2V0], (instregex "^[FSU]CVT[AMNPZ][SU](v4f(16|32)|v4i(16|32)_shift)$",
"^[SU]CVTF(v4f(16|32)|v4i(16|32)_shift)$")>;

// ASIMD FP convert, other, Q-form F16
def : InstRW<[N3Write_6c_4V0], (instregex "^[FSU]CVT[AMNPZ][SU]v8f16$",
Expand Down Expand Up @@ -1241,7 +1241,7 @@ def : InstRW<[N3Write_4c_2V], (instregex "^(FMAX|FMIN)(NM)?Vv4(i16|i32)v$")>;
def : InstRW<[N3Write_6c_3V], (instregex "^(FMAX|FMIN)(NM)?Vv8i16v$")>;

// ASIMD FP multiply
def : InstRW<[N3Wr_FPM], (instregex "^FMULv", "^FMULXv")>;
def : InstRW<[N3Wr_FPM], (instregex "^FMULv", "^FMULX(v|32|64)")>;

// ASIMD FP multiply accumulate
def : InstRW<[N3Wr_FPMA, N3Rd_FPMA], (instregex "^FMLAv", "^FMLSv")>;
Expand Down Expand Up @@ -1330,9 +1330,9 @@ def : InstRW<[N3Write_4c_2V0], (instrs URECPEv4i32, URSQRTEv4i32)>;

// ASIMD reciprocal and square root estimate, D-form F32 and scalar forms
def : InstRW<[N3Write_3c_1V0], (instrs FRECPEv1f16, FRECPEv1i32,
FRECPEv1i64, FRECPEv2f32,
FRECPEv1i64, FRECPEv2f32, FRECPEv2f64,
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@Asher8118 Asher8118 Nov 27, 2025

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While this is D-form, it is not F32, but F64. I could not find a category that fits this instruction, but this felt like the closest group it could belong to.

FRSQRTEv1f16, FRSQRTEv1i32,
FRSQRTEv1i64, FRSQRTEv2f32)>;
FRSQRTEv1i64, FRSQRTEv2f32, FRSQRTEv2f64)>;

// ASIMD reciprocal and square root estimate, D-form F16 and Q-form F32
def : InstRW<[N3Write_4c_2V0], (instrs FRECPEv4f16, FRECPEv4f32,
Expand All @@ -1345,7 +1345,7 @@ def : InstRW<[N3Write_6c_4V0], (instrs FRECPEv8f16, FRSQRTEv8f16)>;
def : InstRW<[N3Write_3c_1V0], (instregex "^FRECPXv")>;

// ASIMD reciprocal step
def : InstRW<[N3Write_4c_1V], (instregex "^FRECPSv", "^FRSQRTSv")>;
def : InstRW<[N3Write_4c_1V], (instregex "^FRECPS(v|32|64)", "^FRSQRTS(v|32|64)")>;

// ASIMD table lookup, 3 table regs
def : InstRW<[N3Write_4c_2V], (instrs TBLv8i8Three, TBLv16i8Three)>;
Expand Down
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