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[AMDGPU] Add support for HW_REG_WAVE_SCHED_MODE #169840

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Merged
merged 2 commits into from
Nov 28, 2025
Merged

[AMDGPU] Add support for HW_REG_WAVE_SCHED_MODE #169840

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7ab6454
[AMDGPU] Add support for HW_REG_WAVE_SCHED_MODE
lancesix Nov 18, 2025
f4742f1
Merge branch 'main' into users/lancesix/sched-mem
lancesix Nov 28, 2025
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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/SIDefines.h
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Original file line number Diff line number Diff line change
Expand Up @@ -523,6 +523,7 @@ enum Id { // HwRegCode, (6) [5:0]
ID_HW_ID1 = 23,
ID_HW_ID2 = 24,
ID_POPS_PACKER = 25,
ID_SCHED_MODE = 26,
ID_PERF_SNAPSHOT_DATA_gfx11 = 27,
ID_IB_STS2 = 28,
ID_SHADER_CYCLES = 29,
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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
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Expand Up @@ -211,6 +211,7 @@ static constexpr CustomOperand Operands[] = {
{{"HW_REG_HW_ID2"}, ID_HW_ID2, isGFX10Plus},
{{"HW_REG_SQ_PERF_SNAPSHOT_PC_HI"}, ID_SQ_PERF_SNAPSHOT_PC_HI, isGFX940},
{{"HW_REG_POPS_PACKER"}, ID_POPS_PACKER, isGFX10},
{{"HW_REG_WAVE_SCHED_MODE"}, ID_SCHED_MODE, isGFX12Plus},
{{"HW_REG_PERF_SNAPSHOT_DATA"}, ID_PERF_SNAPSHOT_DATA_gfx11, isGFX11},
{{"HW_REG_IB_STS2"}, ID_IB_STS2, isGFX1250},
{{"HW_REG_SHADER_CYCLES"}, ID_SHADER_CYCLES, isGFX10_3_GFX11},
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9 changes: 9 additions & 0 deletions llvm/test/MC/AMDGPU/gfx12_asm_sopk.s
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Expand Up @@ -258,3 +258,12 @@ s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES_LO)

s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES_HI)
// GFX12: encoding: [0x1e,0xf8,0x80,0xb8]

s_getreg_b32 s0, hwreg(HW_REG_WAVE_SCHED_MODE)
// GFX12: encoding: [0x1a,0xf8,0x80,0xb8]

s_setreg_b32 hwreg(HW_REG_WAVE_SCHED_MODE, 0, 2), s2
// GFX12: encoding: [0x1a,0x08,0x02,0xb9]

s_setreg_imm32_b32 hwreg(HW_REG_WAVE_SCHED_MODE), 0x2
// GFX12: encoding: [0x1a,0xf8,0x80,0xb9,0x02,0x00,0x00,0x00]
9 changes: 9 additions & 0 deletions llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopk.txt
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Expand Up @@ -276,3 +276,12 @@

# GFX12: s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES_HI) ; encoding: [0x1e,0xf8,0x80,0xb8]
0x1e,0xf8,0x80,0xb8

# GFX12: s_getreg_b32 s0, hwreg(HW_REG_WAVE_SCHED_MODE) ; encoding: [0x1a,0xf8,0x80,0xb8]
0x1a,0xf8,0x80,0xb8

# GFX12: s_setreg_b32 hwreg(HW_REG_WAVE_SCHED_MODE, 0, 2), s2 ; encoding: [0x1a,0x08,0x02,0xb9]
0x1a,0x08,0x02,0xb9

# GFX12: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_SCHED_MODE), 2 ; encoding: [0x1a,0xf8,0x80,0xb9,0x02,0x00,0x00,0x00]
0x1a,0xf8,0x80,0xb9,0x02,0x00,0x00,0x00