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8 changes: 5 additions & 3 deletions llvm/test/tools/llvm-exegesis/RISCV/rvv/filter.test
Original file line number Diff line number Diff line change
@@ -1,7 +1,9 @@
# TODO(mshockwave): We use a fixed seed for this test because sometimes it
# will fail to generate any snippet because it is unable to assign unique
# def and use registers.
# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=inverse_throughput --opcode-name=PseudoVNCLIPU_WX_M1_MASK \
# RUN: --riscv-filter-config='vtype = {VXRM: rod, AVL: VLMAX, SEW: e(8|16), Policy: ta/mu}' --max-configs-per-opcode=1000 --min-instructions=10 | FileCheck %s
# Sometimes it'll fail to generate any snippet because it's unable to assign unique def and use registers.
# ALLOW_RETRIES: 2
# RUN: --riscv-filter-config='vtype = {VXRM: rod, AVL: VLMAX, SEW: e(8|16), Policy: ta/mu}' --max-configs-per-opcode=1000 --min-instructions=10 \
# RUN: -random-generator-seed=5 | FileCheck %s

# CHECK: config: 'vtype = {VXRM: rod, AVL: VLMAX, SEW: e8, Policy: ta/mu}'
# CHECK: config: 'vtype = {VXRM: rod, AVL: VLMAX, SEW: e16, Policy: ta/mu}'
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