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[AMDGPU][SDAG] Add missing cases for SI_INDIRECT_SRC/DST #170323

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Merged
jmmartinez merged 3 commits into from
Dec 11, 2025
Merged

[AMDGPU][SDAG] Add missing cases for SI_INDIRECT_SRC/DST #170323

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33ceb53
Pre commit test: Add <(3, 5, 6, 7) x 32-bit> test cases for insert/ex…
jmmartinez Dec 10, 2025
6e54034
Add llc -O0 line that triggers instruction selection failure
jmmartinez Dec 2, 2025
53a07b2
[AMDGPU][SDAG] Add missing cases for SI_INDIRECT_SRC/DST
jmmartinez Dec 3, 2025
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8 changes: 8 additions & 0 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6304,7 +6304,11 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
}
case AMDGPU::SI_INDIRECT_SRC_V1:
case AMDGPU::SI_INDIRECT_SRC_V2:
case AMDGPU::SI_INDIRECT_SRC_V3:
case AMDGPU::SI_INDIRECT_SRC_V4:
case AMDGPU::SI_INDIRECT_SRC_V5:
case AMDGPU::SI_INDIRECT_SRC_V6:
case AMDGPU::SI_INDIRECT_SRC_V7:
case AMDGPU::SI_INDIRECT_SRC_V8:
case AMDGPU::SI_INDIRECT_SRC_V9:
case AMDGPU::SI_INDIRECT_SRC_V10:
Expand All @@ -6315,7 +6319,11 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
return emitIndirectSrc(MI, *BB, *getSubtarget());
case AMDGPU::SI_INDIRECT_DST_V1:
case AMDGPU::SI_INDIRECT_DST_V2:
case AMDGPU::SI_INDIRECT_DST_V3:
case AMDGPU::SI_INDIRECT_DST_V4:
case AMDGPU::SI_INDIRECT_DST_V5:
case AMDGPU::SI_INDIRECT_DST_V6:
case AMDGPU::SI_INDIRECT_DST_V7:
case AMDGPU::SI_INDIRECT_DST_V8:
case AMDGPU::SI_INDIRECT_DST_V9:
case AMDGPU::SI_INDIRECT_DST_V10:
Expand Down
16 changes: 16 additions & 0 deletions llvm/lib/Target/AMDGPU/SIInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -969,7 +969,11 @@ class SI_INDIRECT_DST<RegisterClass rc> : VPseudoInstSI <

def SI_INDIRECT_SRC_V1 : SI_INDIRECT_SRC<VGPR_32>;
def SI_INDIRECT_SRC_V2 : SI_INDIRECT_SRC<VReg_64>;
def SI_INDIRECT_SRC_V3 : SI_INDIRECT_SRC<VReg_96>;
def SI_INDIRECT_SRC_V4 : SI_INDIRECT_SRC<VReg_128>;
def SI_INDIRECT_SRC_V5 : SI_INDIRECT_SRC<VReg_160>;
def SI_INDIRECT_SRC_V6 : SI_INDIRECT_SRC<VReg_192>;
def SI_INDIRECT_SRC_V7 : SI_INDIRECT_SRC<VReg_224>;
def SI_INDIRECT_SRC_V8 : SI_INDIRECT_SRC<VReg_256>;
def SI_INDIRECT_SRC_V9 : SI_INDIRECT_SRC<VReg_288>;
def SI_INDIRECT_SRC_V10 : SI_INDIRECT_SRC<VReg_320>;
Expand All @@ -980,7 +984,11 @@ def SI_INDIRECT_SRC_V32 : SI_INDIRECT_SRC<VReg_1024>;

def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VGPR_32>;
def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
def SI_INDIRECT_DST_V3 : SI_INDIRECT_DST<VReg_96>;
def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
def SI_INDIRECT_DST_V5 : SI_INDIRECT_DST<VReg_160>;
def SI_INDIRECT_DST_V6 : SI_INDIRECT_DST<VReg_192>;
def SI_INDIRECT_DST_V7 : SI_INDIRECT_DST<VReg_224>;
def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
def SI_INDIRECT_DST_V9 : SI_INDIRECT_DST<VReg_288>;
def SI_INDIRECT_DST_V10 : SI_INDIRECT_DST<VReg_320>;
Expand Down Expand Up @@ -2779,7 +2787,11 @@ multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, string VecSize> {
}

defm : SI_INDIRECT_Pattern <v2f32, f32, "V2">;
defm : SI_INDIRECT_Pattern<v3f32, f32, "V3">;
defm : SI_INDIRECT_Pattern <v4f32, f32, "V4">;
defm : SI_INDIRECT_Pattern<v5f32, f32, "V5">;
defm : SI_INDIRECT_Pattern<v6f32, f32, "V6">;
defm : SI_INDIRECT_Pattern<v7f32, f32, "V7">;
defm : SI_INDIRECT_Pattern <v8f32, f32, "V8">;
defm : SI_INDIRECT_Pattern <v9f32, f32, "V9">;
defm : SI_INDIRECT_Pattern <v10f32, f32, "V10">;
Expand All @@ -2789,7 +2801,11 @@ defm : SI_INDIRECT_Pattern <v16f32, f32, "V16">;
defm : SI_INDIRECT_Pattern <v32f32, f32, "V32">;

defm : SI_INDIRECT_Pattern <v2i32, i32, "V2">;
defm : SI_INDIRECT_Pattern<v3i32, i32, "V3">;
defm : SI_INDIRECT_Pattern <v4i32, i32, "V4">;
defm : SI_INDIRECT_Pattern<v5i32, i32, "V5">;
defm : SI_INDIRECT_Pattern<v6i32, i32, "V6">;
defm : SI_INDIRECT_Pattern<v7i32, i32, "V7">;
defm : SI_INDIRECT_Pattern <v8i32, i32, "V8">;
defm : SI_INDIRECT_Pattern <v9i32, i32, "V9">;
defm : SI_INDIRECT_Pattern <v10i32, i32, "V10">;
Expand Down
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