Skip to content

[RISCV][NFC] Simplify Imm range checks #170497

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
pfusik merged 3 commits into from
Dec 4, 2025
Merged

[RISCV][NFC] Simplify Imm range checks #170497

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
e71c755
[RISCV][NFC] Simplify Imm range checks
pfusik Dec 3, 2025
ca1d13a
[RISCV][NFC] clang-format
pfusik Dec 3, 2025
eb3b594
[RISCV][NFC] Revert `isUInt<N>(Imm) && lowerBoundCond` checks
pfusik Dec 3, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
6 changes: 3 additions & 3 deletions llvm/lib/Target/RISCV/RISCVGISel.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -17,14 +17,14 @@ include "RISCV.td"
include "RISCVCombine.td"

def simm12Plus1 : ImmLeaf<XLenVT, [{
return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]>;
return Imm >= -2047 && Imm <= 2048;}]>;
def simm12Plus1i32 : ImmLeaf<i32, [{
return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]>;
return Imm >= -2047 && Imm <= 2048;}]>;

// FIXME: This doesn't check that the G_CONSTANT we're deriving the immediate
// from is only used once
def simm12Minus1Nonzero : ImmLeaf<XLenVT, [{
return (Imm >= -2049 && Imm < 0) || (Imm > 0 && Imm <= 2046);}]>;
return Imm >= -2049 && Imm <= 2046 && Imm != 0;}]>;

def simm12Minus1NonzeroNonNeg1 : ImmLeaf<XLenVT, [{
return (Imm >= -2049 && Imm < -1) || (Imm > 0 && Imm <= 2046);}]>;
Expand Down
8 changes: 3 additions & 5 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4315,24 +4315,22 @@ bool RISCVDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &SplatVal) {
bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal) {
return selectVSplatImmHelper(
N, SplatVal, *CurDAG, *Subtarget,
[](int64_t Imm) { return (isInt<5>(Imm) && Imm != -16) || Imm == 16; },
[](int64_t Imm) { return Imm >= -15 && Imm <= 16; },
/*Decrement=*/true);
}

bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NoDec(SDValue N, SDValue &SplatVal) {
return selectVSplatImmHelper(
N, SplatVal, *CurDAG, *Subtarget,
[](int64_t Imm) { return (isInt<5>(Imm) && Imm != -16) || Imm == 16; },
[](int64_t Imm) { return Imm >= -15 && Imm <= 16; },
/*Decrement=*/false);
}

bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero(SDValue N,
SDValue &SplatVal) {
return selectVSplatImmHelper(
N, SplatVal, *CurDAG, *Subtarget,
[](int64_t Imm) {
return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);
},
[](int64_t Imm) { return Imm != 0 && Imm >= -15 && Imm <= 16; },
/*Decrement=*/true);
}

Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2904,7 +2904,7 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
Ok = isUInt<5>(Imm) && (Imm > 3);
break;
case RISCVOp::OPERAND_UIMM5_PLUS1:
Ok = (isUInt<5>(Imm) && (Imm != 0)) || (Imm == 32);
Ok = Imm >= 1 && Imm <= 32;
Copy link
Member

@arichardson arichardson Dec 3, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Not sure if that is any better but we couldn't we also do isUInt<5>(Imm - 1) to avoid using these constants?

Copy link
Member

@arichardson arichardson Dec 3, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Either way this is an improvement so LGTM.

Copy link
Collaborator

@topperc topperc Dec 3, 2025 •
edited
Loading

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Not sure if that is any better but we couldn't we also do isUInt<5>(Imm - 1) to avoid using these constants?

You have to do Imm != INT64_MIN && isUInt<5>(Imm - 1) or isUInt<5>((uint64_t)Imm - 1) to avoid UB from signed integer wrapping on the Imm - 1.

Copy link
Member

@arichardson arichardson Dec 4, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Ah yes I guess you could cast to unsigned but that negates the clarity benefit.

break;
case RISCVOp::OPERAND_UIMM6_LSB0:
Ok = isShiftedUInt<5, 1>(Imm);
Expand Down Expand Up @@ -2957,7 +2957,7 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
CASE_OPERAND_SIMM(26)
// clang-format on
case RISCVOp::OPERAND_SIMM5_PLUS1:
Ok = (isInt<5>(Imm) && Imm != -16) || Imm == 16;
Ok = Imm >= -15 && Imm <= 16;
break;
case RISCVOp::OPERAND_SIMM5_NONZERO:
Ok = isInt<5>(Imm) && (Imm != 0);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVInstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -507,7 +507,7 @@ def ixlenimm_li_restricted : Operand<XLenVT> {

// A 12-bit signed immediate plus one where the imm range will be -2047~2048.
def simm12_plus1 : ImmLeaf<XLenVT,
[{return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]>;
[{return Imm >= -2047 && Imm <= 2048;}]>;

// A 6-bit constant greater than 32.
def uimm6gt32 : ImmLeaf<XLenVT, [{
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/RISCV/RISCVInstrInfoV.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -79,19 +79,19 @@ def simm5 : RISCVSImmLeafOp<5> {
}

def simm5_plus1 : RISCVOp, ImmLeaf<XLenVT,
[{return (isInt<5>(Imm) && Imm != -16) || Imm == 16;}]> {
[{return Imm >= -15 && Imm <= 16;}]> {
let ParserMatchClass = SImmAsmOperand<5, "Plus1">;
let OperandType = "OPERAND_SIMM5_PLUS1";
let MCOperandPredicate = [{
int64_t Imm;
if (MCOp.evaluateAsConstantImm(Imm))
return (isInt<5>(Imm) && Imm != -16) || Imm == 16;
return Imm >= -15 && Imm <= 16;
return MCOp.isBareSymbolRef();
}];
}

def simm5_plus1_nonzero : ImmLeaf<XLenVT,
[{return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);}]>;
[{return Imm != 0 && Imm >= -15 && Imm <= 16;}]>;

//===----------------------------------------------------------------------===//
// Scheduling definitions.
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -62,7 +62,7 @@ def UImm5Plus1AsmOperand : AsmOperandClass {
}

def uimm5_plus1 : RISCVOp, ImmLeaf<XLenVT,
[{return (isUInt<5>(Imm) && (Imm != 0)) || (Imm == 32);}]> {
[{return Imm >= 1 && Imm <= 32;}]> {
let ParserMatchClass = UImm5Plus1AsmOperand;
let EncoderMethod = "getImmOpValueMinus1";
let DecoderMethod = "decodeUImmPlus1Operand<5>";
Expand All @@ -71,12 +71,12 @@ def uimm5_plus1 : RISCVOp, ImmLeaf<XLenVT,
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
return false;
return (isUInt<5>(Imm) && (Imm != 0)) || (Imm == 32);
return Imm >= 1 && Imm <= 32;
}];
}

def uimm5ge6_plus1 : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
[{return (Imm >= 6) && (isUInt<5>(Imm) || (Imm == 32));}]> {
[{return Imm >= 6 && Imm <= 32;}]> {
let ParserMatchClass = UImmAsmOperand<5, "GE6Plus1">;
let EncoderMethod = "getImmOpValueMinus1";
let DecoderMethod = "decodeUImmPlus1OperandGE<5,6>";
Expand All @@ -85,7 +85,7 @@ def uimm5ge6_plus1 : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
return false;
return (Imm >= 6) && (isUInt<5>(Imm) || (Imm == 32));
return Imm >= 6 && Imm <= 32;
}];
}

Expand Down