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[RISCV] Add Propeller support for RISC-V #170992

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[RISCV] Add Propeller support for RISC-V #170992

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c906914
[RISCV] Add basic Propeller infrastructure
leidian977 Dec 6, 2025
8d37c32
[RISCV] Add basic Propeller Test
leidian977 Dec 8, 2025
bf8eeb6
[RISCV] update RISCVInstrInfo::insertNoop
leidian977 Dec 8, 2025
e799179
[RISCV] update RISCVInstrInfo::insertNoop
leidian977 Dec 9, 2025
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9 changes: 8 additions & 1 deletion clang/lib/Driver/ToolChains/Clang.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6098,7 +6098,7 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,

if (Arg *A = Args.getLastArg(options::OPT_fbasic_block_address_map,
options::OPT_fno_basic_block_address_map)) {
if ((Triple.isX86() || Triple.isAArch64()) && Triple.isOSBinFormatELF()) {
if ((Triple.isX86() || Triple.isAArch64() || Triple.isRISCV()) && Triple.isOSBinFormatELF()) {
if (A->getOption().matches(options::OPT_fbasic_block_address_map))
A->render(Args, CmdArgs);
} else {
Expand Down Expand Up @@ -6128,6 +6128,13 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
<< A->getAsString(Args) << A->getValue();
else
A->render(Args, CmdArgs);
} else if (Triple.isRISCV() && Triple.isOSBinFormatELF()) {
// Add RISC-V support for basic block sections
if (Val != "labels" && Val != "none" && !Val.starts_with("list="))
D.Diag(diag::err_drv_invalid_value)
<< A->getAsString(Args) << A->getValue();
else
A->render(Args, CmdArgs);
} else if (Triple.isNVPTX()) {
// Do not pass the option to the GPU compilation. We still want it enabled
// for the host-side compilation, so seeing it here is not an error.
Expand Down
1 change: 1 addition & 0 deletions clang/test/Driver/basic-block-address-map.c
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Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
// RUN: %clang -### --target=x86_64 -fbasic-block-address-map %s -S 2>&1 | FileCheck -check-prefix=CHECK-PRESENT %s
// RUN: %clang -### --target=aarch64 -fbasic-block-address-map %s -S 2>&1 | FileCheck -check-prefix=CHECK-PRESENT %s
// RUN: %clang -### --target=riscv64 -fbasic-block-address-map %s -S 2>&1 | FileCheck -check-prefix=CHECK-PRESENT %s
// CHECK-PRESENT: -fbasic-block-address-map

// RUN: %clang -### --target=x86_64 -fno-basic-block-address-map %s -S 2>&1 | FileCheck %s --check-prefix=CHECK-ABSENT
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5 changes: 5 additions & 0 deletions clang/test/Driver/fbasic-block-sections.c
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Expand Up @@ -9,6 +9,11 @@
// RUN: not %clang -c --target=arm-unknown-linux -fbasic-block-sections=all %s -S 2>&1 | FileCheck -check-prefix=CHECK-TRIPLE %s
// RUN: %clang -### --target=arm-unknown-linux -fbasic-block-sections=all -fbasic-block-sections=none %s -S 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-NOOPT %s
// RUN: %clang -### --target=riscv64 -fbasic-block-sections=none %s -S 2>&1 | FileCheck -check-prefix=CHECK-OPT-NONE %s
// RUN: %clang -### --target=riscv64 -fbasic-block-sections=list=%s %s -S 2>&1 | FileCheck -check-prefix=CHECK-OPT-LIST %s
// RUN: %clang -### --target=riscv64 -fbasic-block-sections=labels %s -S 2>&1 | FileCheck -check-prefix=CHECK-OPT-LABELS %s
// RUN: not %clang -### --target=riscv64 -fbasic-block-sections=all %s -S 2>&1 | FileCheck -check-prefix=CHECK-INVALID-VALUE %s
// RUN: not %clang -c --target=riscv64-unknown-linux -fbasic-block-sections=all %s -S 2>&1 | FileCheck -check-prefix=CHECK-INVALID-VALUE %s
// RUN: not %clang -c --target=x86_64-apple-darwin10 -fbasic-block-sections=all %s -S 2>&1 | FileCheck -check-prefix=CHECK-TRIPLE %s
// RUN: not %clang -### --target=x86_64 -fbasic-block-sections=alll %s -S 2>&1 | FileCheck -check-prefix=CHECK-INVALID-VALUE %s
// RUN: not %clang -### --target=x86_64 -fbasic-block-sections=list %s -S 2>&1 | FileCheck -check-prefix=CHECK-INVALID-VALUE %s
Expand Down
12 changes: 12 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Expand Up @@ -89,6 +89,18 @@ RISCVInstrInfo::RISCVInstrInfo(const RISCVSubtarget &STI)
#define GET_INSTRINFO_HELPERS
#include "RISCVGenInstrInfo.inc"

void RISCVInstrInfo::insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
DebugLoc DL;
if (STI.hasStdExtZca())
BuildMI(MBB, MI, DL, get(RISCV::C_NOP));
else
BuildMI(MBB, MI, DL, get(RISCV::ADDI))
.addReg(RISCV::X0)
.addReg(RISCV::X0)
.addImm(0);
}

MCInst RISCVInstrInfo::getNop() const {
if (STI.hasStdExtZca())
return MCInstBuilder(RISCV::C_NOP);
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -86,6 +86,9 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {

const RISCVRegisterInfo &getRegisterInfo() const { return RegInfo; }

void insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const override;

MCInst getNop() const override;

Register isLoadFromStackSlot(const MachineInstr &MI,
Expand Down