Skip to content

[RISCV] Combine (addi (addi)) and add post riscv-opt-w-instrs machine-combiner #171165

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
pfusik wants to merge 7 commits into
base: main
Choose a base branch
from
Open

[RISCV] Combine (addi (addi)) and add post riscv-opt-w-instrs machine-combiner #171165

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
7 commits
Select commit Hold shift + click to select a range
10731b2
[RISCV][test] Add tests for (addi (addi X, C1), C2) -> (addi X, C1+C2…
pfusik Dec 8, 2025
94430e2
[RISCV][test] Add a test for post opt-w-instrs MachineCombiner
pfusik Dec 8, 2025
ea5d1fe
[RISCV] Combine (addi (addi X, C1), C2) -> (addi X, C1+C2)
pfusik Dec 8, 2025
dbb75f0
[RISCV] Add post opt-w-instrs MachineCombiner
pfusik Dec 8, 2025
2dc1d2a
[RISCV][NFC] clang-format
pfusik Dec 8, 2025
70618ca
[RISCV] Remove the first MachineCombiner pass
pfusik Dec 9, 2025
6055a4a
[RISCV][NFC] Make the machine combiner functions members of `RISCVIns…
pfusik Dec 9, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
68 changes: 54 additions & 14 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2654,6 +2654,22 @@ static bool getSHXADDPatterns(const MachineInstr &Root,
return Found;
}

// Check (addi (addi X, C1), C2) -> (addi X, C1+C2) pattern.
static bool getADDIADDIPatterns(const MachineInstr &Root,
SmallVectorImpl<unsigned> &Patterns) {
if (Root.getOpcode() != RISCV::ADDI)
return false;
const MachineBasicBlock &MBB = *Root.getParent();
const MachineInstr *Inner = canCombine(MBB, Root.getOperand(1), RISCV::ADDI);
if (!Inner || !Inner->getOperand(1).isReg())
return false;
int64_t Sum = Inner->getOperand(2).getImm() + Root.getOperand(2).getImm();
if (!isInt<12>(Sum))
return false;
Patterns.push_back(RISCVMachineCombinerPattern::ADDI_ADDI);
return true;
}

CombinerObjective RISCVInstrInfo::getCombinerObjective(unsigned Pattern) const {
switch (Pattern) {
case RISCVMachineCombinerPattern::FMADD_AX:
Expand All @@ -2676,6 +2692,9 @@ bool RISCVInstrInfo::getMachineCombinerPatterns(
if (getSHXADDPatterns(Root, Patterns))
return true;

if (getADDIADDIPatterns(Root, Patterns))
return true;

return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns,
DoRegPressureReduce);
}
Expand Down Expand Up @@ -2715,13 +2734,12 @@ static unsigned getAddendOperandIdx(unsigned Pattern) {
}
}

static void combineFPFusedMultiply(MachineInstr &Root, MachineInstr &Prev,
unsigned Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs) {
void RISCVInstrInfo::combineFPFusedMultiply(
MachineInstr &Root, MachineInstr &Prev, unsigned Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs) const {
MachineFunction *MF = Root.getMF();
MachineRegisterInfo &MRI = MF->getRegInfo();
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();

MachineOperand &Mul1 = Prev.getOperand(1);
MachineOperand &Mul2 = Prev.getOperand(2);
Expand All @@ -2745,7 +2763,7 @@ static void combineFPFusedMultiply(MachineInstr &Root, MachineInstr &Prev,
MRI.clearKillFlags(Mul2.getReg());

MachineInstrBuilder MIB =
BuildMI(*MF, MergedLoc, TII->get(FusedOpc), DstReg)
BuildMI(*MF, MergedLoc, get(FusedOpc), DstReg)
.addReg(Mul1.getReg(), getKillRegState(Mul1IsKill))
.addReg(Mul2.getReg(), getKillRegState(Mul2IsKill))
.addReg(Addend.getReg(), getKillRegState(AddendIsKill))
Expand All @@ -2760,14 +2778,13 @@ static void combineFPFusedMultiply(MachineInstr &Root, MachineInstr &Prev,
// Combine patterns like (sh3add Z, (add X, (slli Y, 5))) to
// (sh3add (sh2add Y, Z), X) if the shift amount can be split across two
// shXadd instructions. The outer shXadd keeps its original opcode.
static void
genShXAddAddShift(MachineInstr &Root, unsigned AddOpIdx,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<Register, unsigned> &InstrIdxForVirtReg) {
void RISCVInstrInfo::genShXAddAddShift(
MachineInstr &Root, unsigned AddOpIdx,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<Register, unsigned> &InstrIdxForVirtReg) const {
MachineFunction *MF = Root.getMF();
MachineRegisterInfo &MRI = MF->getRegInfo();
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();

unsigned OuterShiftAmt = getSHXADDShiftAmount(Root.getOpcode());
assert(OuterShiftAmt != 0 && "Unexpected opcode");
Expand Down Expand Up @@ -2803,10 +2820,10 @@ genShXAddAddShift(MachineInstr &Root, unsigned AddOpIdx,

Register NewVR = MRI.createVirtualRegister(&RISCV::GPRRegClass);

auto MIB1 = BuildMI(*MF, MIMetadata(Root), TII->get(InnerOpc), NewVR)
auto MIB1 = BuildMI(*MF, MIMetadata(Root), get(InnerOpc), NewVR)
.addReg(Y.getReg(), getKillRegState(Y.isKill()))
.addReg(Z.getReg(), getKillRegState(Z.isKill()));
auto MIB2 = BuildMI(*MF, MIMetadata(Root), TII->get(Root.getOpcode()),
auto MIB2 = BuildMI(*MF, MIMetadata(Root), get(Root.getOpcode()),
Root.getOperand(0).getReg())
.addReg(NewVR, RegState::Kill)
.addReg(X.getReg(), getKillRegState(X.isKill()));
Expand All @@ -2819,6 +2836,26 @@ genShXAddAddShift(MachineInstr &Root, unsigned AddOpIdx,
DelInstrs.push_back(&Root);
}

// Fold (addi (addi X, C1), C2) -> (addi X, C1+C2)
void RISCVInstrInfo::combineADDIADDI(
MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs) const {
MachineFunction *MF = Root.getMF();
MachineRegisterInfo &MRI = MF->getRegInfo();

MachineInstr *Inner = MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
const MachineOperand &X = Inner->getOperand(1);
int64_t Sum = Inner->getOperand(2).getImm() + Root.getOperand(2).getImm();

auto MIB = BuildMI(*MF, MIMetadata(Root), get(RISCV::ADDI),
Root.getOperand(0).getReg())
.addReg(X.getReg(), getKillRegState(X.isKill()))
.addImm(Sum);
InsInstrs.push_back(MIB);
DelInstrs.push_back(Inner);
DelInstrs.push_back(&Root);
}

void RISCVInstrInfo::genAlternativeCodeSequence(
MachineInstr &Root, unsigned Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
Expand Down Expand Up @@ -2848,6 +2885,9 @@ void RISCVInstrInfo::genAlternativeCodeSequence(
case RISCVMachineCombinerPattern::SHXADD_ADD_SLLI_OP2:
genShXAddAddShift(Root, 2, InsInstrs, DelInstrs, InstrIdxForVirtReg);
return;
case RISCVMachineCombinerPattern::ADDI_ADDI:
combineADDIADDI(Root, InsInstrs, DelInstrs);
return;
}
}

Expand Down
13 changes: 13 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -76,6 +76,7 @@ enum RISCVMachineCombinerPattern : unsigned {
FNMSUB,
SHXADD_ADD_SLLI_OP1,
SHXADD_ADD_SLLI_OP2,
ADDI_ADDI,
};

class RISCVInstrInfo : public RISCVGenInstrInfo {
Expand Down Expand Up @@ -355,6 +356,18 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
const MachineInstr &MI2) const;
bool hasReassociableVectorSibling(const MachineInstr &Inst,
bool &Commuted) const;
void combineFPFusedMultiply(MachineInstr &Root, MachineInstr &Prev,
unsigned Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs) const;
void
genShXAddAddShift(MachineInstr &Root, unsigned AddOpIdx,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<Register, unsigned> &InstrIdxForVirtReg) const;
void combineADDIADDI(MachineInstr &Root,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs) const;
};

namespace RISCV {
Expand Down
10 changes: 2 additions & 8 deletions llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -404,7 +404,6 @@ class RISCVPassConfig : public TargetPassConfig {
void addPreRegAlloc() override;
void addPostRegAlloc() override;
void addFastRegAlloc() override;
bool addILPOpts() override;

std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
};
Expand Down Expand Up @@ -598,6 +597,8 @@ void RISCVPassConfig::addMachineSSAOptimization() {
if (TM->getTargetTriple().isRISCV64()) {
addPass(createRISCVOptWInstrsPass());
}
if (EnableMachineCombiner)
addPass(&MachineCombinerID);
}

void RISCVPassConfig::addPreRegAlloc() {
Expand Down Expand Up @@ -631,13 +632,6 @@ void RISCVPassConfig::addPostRegAlloc() {
addPass(createRISCVRedundantCopyEliminationPass());
}

bool RISCVPassConfig::addILPOpts() {
if (EnableMachineCombiner)
addPass(&MachineCombinerID);

return true;
}

void RISCVTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
#define GET_PASS_REGISTRY "RISCVPassRegistry.def"
#include "llvm/Passes/TargetPassRegistry.inc"
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1238,10 +1238,10 @@ define i1 @fpclass(float %x) {
; RV64I-NEXT: sltu a4, a5, a4
; RV64I-NEXT: and a3, a3, a0
; RV64I-NEXT: or a2, a2, a6
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: and a0, a4, a0
; RV64I-NEXT: or a2, a2, a3
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
%cmp = call i1 @llvm.is.fpclass.f32(float %x, i32 639)
ret i1 %cmp
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/O3-pipeline.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -110,9 +110,6 @@
; CHECK-NEXT: Remove dead machine instructions
; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: Machine Natural Loop Construction
; CHECK-NEXT: Machine Trace Metrics
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine InstCombiner
; CHECK-NEXT: Machine Block Frequency Analysis
; CHECK-NEXT: Early Machine Loop Invariant Code Motion
; CHECK-NEXT: MachineDominator Tree Construction
Expand All @@ -124,6 +121,9 @@
; CHECK-NEXT: Peephole Optimizations
; CHECK-NEXT: Remove dead machine instructions
; RV64-NEXT: RISC-V Optimize W Instructions
; CHECK-NEXT: Machine Trace Metrics
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine InstCombiner
; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
; CHECK-NEXT: RISC-V Merge Base Offset
; CHECK-NEXT: MachineDominator Tree Construction
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -58,11 +58,11 @@ define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i128 %d, i32 %e, i32 %f,
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: add a0, a0, a5
; RV64I-NEXT: xor a1, a4, t1
; RV64I-NEXT: add a0, a0, a6
; RV64I-NEXT: or a1, a3, a1
; RV64I-NEXT: seqz a1, a1
; RV64I-NEXT: add a0, a0, t0
; RV64I-NEXT: addw a0, a1, a0
; RV64I-NEXT: add a0, a0, a6
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: addw a0, a0, t0
; RV64I-NEXT: ret
%a_ext = zext i8 %a to i32
%b_ext = zext i16 %b to i32
Expand Down
Loading