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[AMDGPU][NFC] dump Waitcnt using an ostream operator #171251

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Merged
ssahasra merged 2 commits into from
Dec 10, 2025
+29 −2
Merged

[AMDGPU][NFC] dump Waitcnt using an ostream operator #171251

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038b553
[AMDGPU][NFC] dump Waitcnt using an ostream operator
ssahasra Dec 9, 2025
854c902
clean up whitespace; introduce an actual use of the operator
ssahasra Dec 9, 2025
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1 change: 1 addition & 0 deletions llvm/include/llvm/ADT/StringExtras.h
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Original file line number Diff line number Diff line change
Expand Up @@ -541,6 +541,7 @@ class ListSeparator {
}
return Separator;
}
bool unused() { return First; }
};

/// A forward iterator over partitions of string over a separator.
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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
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Expand Up @@ -1451,9 +1451,9 @@ bool WaitcntGeneratorPreGFX12::applyPreexistingWaitcnt(
} else if (Opcode == AMDGPU::S_WAITCNT_lds_direct) {
assert(ST->hasVMemToLDSLoad());
LLVM_DEBUG(dbgs() << "Processing S_WAITCNT_lds_direct: " << II
<< "Before: " << Wait.LoadCnt << '\n';);
<< "Before: " << Wait;);
ScoreBrackets.determineWait(LOAD_CNT, FIRST_LDS_VGPR, Wait);
LLVM_DEBUG(dbgs() << "After: " << Wait.LoadCnt << '\n';);
LLVM_DEBUG(dbgs() << "After: " << Wait;);

// It is possible (but unlikely) that this is the only wait instruction,
// in which case, we exit this loop without a WaitcntInstr to consume
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24 changes: 24 additions & 0 deletions llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
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Expand Up @@ -1712,6 +1712,30 @@ bool hasValueInRangeLikeMetadata(const MDNode &MD, int64_t Val) {
return false;
}

raw_ostream &operator<<(raw_ostream &OS, const AMDGPU::Waitcnt &Wait) {
ListSeparator LS;
if (Wait.LoadCnt != ~0u)
OS << LS << "LoadCnt: " << Wait.LoadCnt;
if (Wait.ExpCnt != ~0u)
OS << LS << "ExpCnt: " << Wait.ExpCnt;
if (Wait.DsCnt != ~0u)
OS << LS << "DsCnt: " << Wait.DsCnt;
if (Wait.StoreCnt != ~0u)
OS << LS << "StoreCnt: " << Wait.StoreCnt;
if (Wait.SampleCnt != ~0u)
OS << LS << "SampleCnt: " << Wait.SampleCnt;
if (Wait.BvhCnt != ~0u)
OS << LS << "BvhCnt: " << Wait.BvhCnt;
if (Wait.KmCnt != ~0u)
OS << LS << "KmCnt: " << Wait.KmCnt;
if (Wait.XCnt != ~0u)
OS << LS << "XCnt: " << Wait.XCnt;
if (LS.unused())
OS << "none";
OS << '\n';
return OS;
}

unsigned getVmcntBitMask(const IsaVersion &Version) {
return (1 << (getVmcntBitWidthLo(Version.Major) +
getVmcntBitWidthHi(Version.Major))) -
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2 changes: 2 additions & 0 deletions llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
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Expand Up @@ -1119,6 +1119,8 @@ struct Waitcnt {
std::min(SampleCnt, Other.SampleCnt), std::min(BvhCnt, Other.BvhCnt),
std::min(KmCnt, Other.KmCnt), std::min(XCnt, Other.XCnt));
}

friend raw_ostream &operator<<(raw_ostream &OS, const AMDGPU::Waitcnt &Wait);
};

// The following methods are only meaningful on targets that support
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