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release/21.x: [Mips] Support "$sp" named register (#136821) #171297

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@llvmbot llvmbot commented Dec 9, 2025

Backport 13012fe

Requested by: @brad0

@llvmbot llvmbot added this to the LLVM 21.x Release milestone Dec 9, 2025
@github-project-automation github-project-automation bot moved this to Needs Triage in LLVM Release Status Dec 9, 2025
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llvmbot commented Dec 9, 2025

@yingopq What do you think about merging this PR to the release branch?

@llvmbot llvmbot requested a review from yingopq December 9, 2025 08:35
@llvmbot llvmbot mentioned this pull request Dec 9, 2025
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llvmbot commented Dec 9, 2025

@llvm/pr-subscribers-backend-mips

Author: None (llvmbot)

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Backport 13012fe

Requested by: @brad0

Patch is 25.86 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/171297.diff

5 Files Affected:

  • (modified) llvm/lib/Target/Mips/MipsISelLowering.cpp (+90-12)
  • (modified) llvm/lib/Target/Mips/MipsISelLowering.h (+2)
  • (modified) llvm/test/CodeGen/Mips/named-register-n32.ll (+277-10)
  • (modified) llvm/test/CodeGen/Mips/named-register-n64.ll (+277-10)
  • (modified) llvm/test/CodeGen/Mips/named-register-o32.ll (+278-11)
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index ec6b382151660..257fbddb498ad 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -72,6 +72,8 @@
 #include <cstdint>
 #include <deque>
 #include <iterator>
+#include <regex>
+#include <string>
 #include <utility>
 #include <vector>
 
@@ -4929,25 +4931,101 @@ MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI,
   return BB;
 }
 
+// Copies the function MipsAsmParser::matchCPURegisterName.
+int MipsTargetLowering::getCPURegisterIndex(StringRef Name) const {
+  int CC;
+
+  CC = StringSwitch<unsigned>(Name)
+           .Case("zero", 0)
+           .Case("at", 1)
+           .Case("AT", 1)
+           .Case("a0", 4)
+           .Case("a1", 5)
+           .Case("a2", 6)
+           .Case("a3", 7)
+           .Case("v0", 2)
+           .Case("v1", 3)
+           .Case("s0", 16)
+           .Case("s1", 17)
+           .Case("s2", 18)
+           .Case("s3", 19)
+           .Case("s4", 20)
+           .Case("s5", 21)
+           .Case("s6", 22)
+           .Case("s7", 23)
+           .Case("k0", 26)
+           .Case("k1", 27)
+           .Case("gp", 28)
+           .Case("sp", 29)
+           .Case("fp", 30)
+           .Case("s8", 30)
+           .Case("ra", 31)
+           .Case("t0", 8)
+           .Case("t1", 9)
+           .Case("t2", 10)
+           .Case("t3", 11)
+           .Case("t4", 12)
+           .Case("t5", 13)
+           .Case("t6", 14)
+           .Case("t7", 15)
+           .Case("t8", 24)
+           .Case("t9", 25)
+           .Default(-1);
+
+  if (!(ABI.IsN32() || ABI.IsN64()))
+    return CC;
+
+  // Although SGI documentation just cuts out t0-t3 for n32/n64,
+  // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7
+  // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7.
+  if (8 <= CC && CC <= 11)
+    CC += 4;
+
+  if (CC == -1)
+    CC = StringSwitch<unsigned>(Name)
+             .Case("a4", 8)
+             .Case("a5", 9)
+             .Case("a6", 10)
+             .Case("a7", 11)
+             .Case("kt0", 26)
+             .Case("kt1", 27)
+             .Default(-1);
+
+  return CC;
+}
+
 // FIXME? Maybe this could be a TableGen attribute on some registers and
 // this table could be generated automatically from RegInfo.
 Register
 MipsTargetLowering::getRegisterByName(const char *RegName, LLT VT,
                                       const MachineFunction &MF) const {
-  // The Linux kernel uses $28 and sp.
-  if (Subtarget.isGP64bit()) {
-    Register Reg = StringSwitch<Register>(RegName)
-                       .Case("$28", Mips::GP_64)
-                       .Case("sp", Mips::SP_64)
-                       .Default(Register());
-    return Reg;
+  // 1. Delete symbol '$'.
+  std::string newRegName = RegName;
+  if (StringRef(RegName).starts_with("$"))
+    newRegName = StringRef(RegName).substr(1);
+
+  // 2. Get register index value.
+  std::smatch matchResult;
+  int regIdx;
+  static const std::regex matchStr("^[0-9]*$");
+  if (std::regex_match(newRegName, matchResult, matchStr))
+    regIdx = std::stoi(newRegName);
+  else {
+    newRegName = StringRef(newRegName).lower();
+    regIdx = getCPURegisterIndex(StringRef(newRegName));
+  }
+
+  // 3. Get register.
+  if (regIdx >= 0 && regIdx < 32) {
+    const MCRegisterInfo *MRI = MF.getContext().getRegisterInfo();
+    const MCRegisterClass &RC = Subtarget.isGP64bit()
+                                    ? MRI->getRegClass(Mips::GPR64RegClassID)
+                                    : MRI->getRegClass(Mips::GPR32RegClassID);
+    return RC.getRegister(regIdx);
   }
 
-  Register Reg = StringSwitch<Register>(RegName)
-                     .Case("$28", Mips::GP)
-                     .Case("sp", Mips::SP)
-                     .Default(Register());
-  return Reg;
+  report_fatal_error(
+      Twine("Invalid register name \"" + StringRef(RegName) + "\"."));
 }
 
 MachineBasicBlock *MipsTargetLowering::emitLDR_W(MachineInstr &MI,
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.h b/llvm/lib/Target/Mips/MipsISelLowering.h
index c65c76ccffc75..09a59905c8c25 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.h
+++ b/llvm/lib/Target/Mips/MipsISelLowering.h
@@ -718,6 +718,8 @@ class TargetRegisterClass;
       return true;
     }
 
+    int getCPURegisterIndex(StringRef Name) const;
+
     /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
     MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI,
                                                 MachineBasicBlock *BB,
diff --git a/llvm/test/CodeGen/Mips/named-register-n32.ll b/llvm/test/CodeGen/Mips/named-register-n32.ll
index 112e04e14b2ac..b8aaec6bf2aec 100644
--- a/llvm/test/CodeGen/Mips/named-register-n32.ll
+++ b/llvm/test/CodeGen/Mips/named-register-n32.ll
@@ -1,29 +1,296 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=mips64 -relocation-model=static -mattr=+noabicalls \
+; RUN: llc -mtriple=mips64 -relocation-model=static -O0 -mattr=+noabicalls \
 ; RUN:   -target-abi n32 < %s | FileCheck %s
 
 declare i64 @llvm.read_register.i64(metadata)
 
-define i64 @get_gp() {
-; CHECK-LABEL: get_gp:
+define i64 @get_zero() {
+; CHECK-LABEL: get_zero:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $zero
+  %1 = call i64 @llvm.read_register.i64(metadata !0)
+  ret i64 %1
+}
+
+define i64 @get_at() {
+; CHECK-LABEL: get_at:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $1
+  %1 = call i64 @llvm.read_register.i64(metadata !1)
+  ret i64 %1
+}
+
+define i64 @get_v0() {
+; CHECK-LABEL: get_v0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    jr $ra
+  %1 = call i64 @llvm.read_register.i64(metadata !2)
+  ret i64 %1
+}
+
+define i64 @get_v1() {
+; CHECK-LABEL: get_v1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $3
+  %1 = call i64 @llvm.read_register.i64(metadata !3)
+  ret i64 %1
+}
+
+define i64 @get_a0() {
+; CHECK-LABEL: get_a0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $4
+  %1 = call i64 @llvm.read_register.i64(metadata !4)
+  ret i64 %1
+}
+
+define i64 @get_a1() {
+; CHECK-LABEL: get_a1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $5
+  %1 = call i64 @llvm.read_register.i64(metadata !5)
+  ret i64 %1
+}
+
+define i64 @get_a2() {
+; CHECK-LABEL: get_a2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $6
+  %1 = call i64 @llvm.read_register.i64(metadata !6)
+  ret i64 %1
+}
+
+define i64 @get_a3() {
+; CHECK-LABEL: get_a3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $7
+  %1 = call i64 @llvm.read_register.i64(metadata !7)
+  ret i64 %1
+}
+
+define i64 @get_t0() {
+; CHECK-LABEL: get_t0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $12
+  %1 = call i64 @llvm.read_register.i64(metadata !8)
+  ret i64 %1
+}
+
+define i64 @get_t1() {
+; CHECK-LABEL: get_t1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $13
+  %1 = call i64 @llvm.read_register.i64(metadata !9)
+  ret i64 %1
+}
+
+define i64 @get_t2() {
+; CHECK-LABEL: get_t2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $14
+  %1 = call i64 @llvm.read_register.i64(metadata !10)
+  ret i64 %1
+}
+
+define i64 @get_t3() {
+; CHECK-LABEL: get_t3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $15
+  %1 = call i64 @llvm.read_register.i64(metadata !11)
+  ret i64 %1
+}
+
+define i64 @get_t4() {
+; CHECK-LABEL: get_t4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $12
+  %1 = call i64 @llvm.read_register.i64(metadata !12)
+  ret i64 %1
+}
+
+define i64 @get_t5() {
+; CHECK-LABEL: get_t5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $13
+  %1 = call i64 @llvm.read_register.i64(metadata !13)
+  ret i64 %1
+}
+
+define i64 @get_t6() {
+; CHECK-LABEL: get_t6:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $14
+  %1 = call i64 @llvm.read_register.i64(metadata !14)
+  ret i64 %1
+}
+
+define i64 @get_t7() {
+; CHECK-LABEL: get_t7:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $15
+  %1 = call i64 @llvm.read_register.i64(metadata !15)
+  ret i64 %1
+}
+
+define i64 @get_s0() {
+; CHECK-LABEL: get_s0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $16
+  %1 = call i64 @llvm.read_register.i64(metadata !16)
+  ret i64 %1
+}
+
+define i64 @get_s1() {
+; CHECK-LABEL: get_s1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $17
+  %1 = call i64 @llvm.read_register.i64(metadata !17)
+  ret i64 %1
+}
+
+define i64 @get_s2() {
+; CHECK-LABEL: get_s2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $18
+  %1 = call i64 @llvm.read_register.i64(metadata !18)
+  ret i64 %1
+}
+
+define i64 @get_s3() {
+; CHECK-LABEL: get_s3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $19
+  %1 = call i64 @llvm.read_register.i64(metadata !19)
+  ret i64 %1
+}
+
+define i64 @get_s4() {
+; CHECK-LABEL: get_s4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $20
+  %1 = call i64 @llvm.read_register.i64(metadata !20)
+  ret i64 %1
+}
+
+define i64 @get_s5() {
+; CHECK-LABEL: get_s5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $21
+  %1 = call i64 @llvm.read_register.i64(metadata !21)
+  ret i64 %1
+}
+
+define i64 @get_s6() {
+; CHECK-LABEL: get_s6:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $22
+  %1 = call i64 @llvm.read_register.i64(metadata !22)
+  ret i64 %1
+}
+
+define i64 @get_s7() {
+; CHECK-LABEL: get_s7:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $23
+  %1 = call i64 @llvm.read_register.i64(metadata !23)
+  ret i64 %1
+}
+
+define i64 @get_t8() {
+; CHECK-LABEL: get_t8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $24
+  %1 = call i64 @llvm.read_register.i64(metadata !24)
+  ret i64 %1
+}
+
+define i64 @get_t9() {
+; CHECK-LABEL: get_t9:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $25
+  %1 = call i64 @llvm.read_register.i64(metadata !25)
+  ret i64 %1
+}
+
+define i64 @get_k0() {
+; CHECK-LABEL: get_k0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $26
+  %1 = call i64 @llvm.read_register.i64(metadata !26)
+  ret i64 %1
+}
+
+define i64 @get_k1() {
+; CHECK-LABEL: get_k1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $27
+  %1 = call i64 @llvm.read_register.i64(metadata !27)
+  ret i64 %1
+}
+
+define i64 @get_$gp() {
+; CHECK-LABEL: get_$gp:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    move $2, $gp
-  %1 = call i64 @llvm.read_register.i64(metadata !0)
+  %1 = call i64 @llvm.read_register.i64(metadata !28)
   ret i64 %1
 }
 
 define i64 @get_sp() {
 ; CHECK-LABEL: get_sp:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    jr $ra
 ; CHECK-NEXT:    move $2, $sp
-  %1 = call i64 @llvm.read_register.i64(metadata !1)
+  %1 = call i64 @llvm.read_register.i64(metadata !29)
+  ret i64 %1
+}
+
+define i64 @get_fp() {
+; CHECK-LABEL: get_fp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $fp
+  %1 = call i64 @llvm.read_register.i64(metadata !30)
+  ret i64 %1
+}
+
+define i64 @get_ra() {
+; CHECK-LABEL: get_ra:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $ra
+  %1 = call i64 @llvm.read_register.i64(metadata !31)
   ret i64 %1
 }
 
-!llvm.named.register.$28 = !{!0}
-!llvm.named.register.sp = !{!1}
+!llvm.named.register = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15, !16, !17, !18, !19, !20, !21, !22, !23, !24, !25, !26, !27, !28, !29, !30, !31}
 
-!0 = !{!"$28"}
-!1 = !{!"sp"}
+!0 = !{!"$zero"}
+!1 = !{!"$at"}
+!2 = !{!"$v0"}
+!3 = !{!"$v1"}
+!4 = !{!"$a0"}
+!5 = !{!"$a1"}
+!6 = !{!"$a2"}
+!7 = !{!"$a3"}
+!8 = !{!"$t0"}
+!9 = !{!"$t1"}
+!10 = !{!"$t2"}
+!11 = !{!"$t3"}
+!12 = !{!"$t4"}
+!13 = !{!"$t5"}
+!14 = !{!"$t6"}
+!15 = !{!"$t7"}
+!16 = !{!"$s0"}
+!17 = !{!"$s1"}
+!18 = !{!"$s2"}
+!19 = !{!"$s3"}
+!20 = !{!"$s4"}
+!21 = !{!"$s5"}
+!22 = !{!"$s6"}
+!23 = !{!"$s7"}
+!24 = !{!"$t8"}
+!25 = !{!"$t9"}
+!26 = !{!"$k0"}
+!27 = !{!"$k1"}
+!28 = !{!"$gp"}
+!29 = !{!"$sp"}
+!30 = !{!"$fp"}
+!31 = !{!"$ra"}
diff --git a/llvm/test/CodeGen/Mips/named-register-n64.ll b/llvm/test/CodeGen/Mips/named-register-n64.ll
index 42d9ba1e1f15c..487d43708d148 100644
--- a/llvm/test/CodeGen/Mips/named-register-n64.ll
+++ b/llvm/test/CodeGen/Mips/named-register-n64.ll
@@ -1,29 +1,296 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=mips64 -relocation-model=static -mattr=+noabicalls \
+; RUN: llc -mtriple=mips64 -relocation-model=static -O0 -mattr=+noabicalls \
 ; RUN:   < %s | FileCheck %s
 
 declare i64 @llvm.read_register.i64(metadata)
 
-define i64 @get_gp() {
-; CHECK-LABEL: get_gp:
+define i64 @get_zero() {
+; CHECK-LABEL: get_zero:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $zero
+  %1 = call i64 @llvm.read_register.i64(metadata !0)
+  ret i64 %1
+}
+
+define i64 @get_at() {
+; CHECK-LABEL: get_at:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $1
+  %1 = call i64 @llvm.read_register.i64(metadata !1)
+  ret i64 %1
+}
+
+define i64 @get_v0() {
+; CHECK-LABEL: get_v0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    jr $ra
+  %1 = call i64 @llvm.read_register.i64(metadata !2)
+  ret i64 %1
+}
+
+define i64 @get_v1() {
+; CHECK-LABEL: get_v1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $3
+  %1 = call i64 @llvm.read_register.i64(metadata !3)
+  ret i64 %1
+}
+
+define i64 @get_a0() {
+; CHECK-LABEL: get_a0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $4
+  %1 = call i64 @llvm.read_register.i64(metadata !4)
+  ret i64 %1
+}
+
+define i64 @get_a1() {
+; CHECK-LABEL: get_a1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $5
+  %1 = call i64 @llvm.read_register.i64(metadata !5)
+  ret i64 %1
+}
+
+define i64 @get_a2() {
+; CHECK-LABEL: get_a2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $6
+  %1 = call i64 @llvm.read_register.i64(metadata !6)
+  ret i64 %1
+}
+
+define i64 @get_a3() {
+; CHECK-LABEL: get_a3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $7
+  %1 = call i64 @llvm.read_register.i64(metadata !7)
+  ret i64 %1
+}
+
+define i64 @get_t0() {
+; CHECK-LABEL: get_t0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $12
+  %1 = call i64 @llvm.read_register.i64(metadata !8)
+  ret i64 %1
+}
+
+define i64 @get_t1() {
+; CHECK-LABEL: get_t1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $13
+  %1 = call i64 @llvm.read_register.i64(metadata !9)
+  ret i64 %1
+}
+
+define i64 @get_t2() {
+; CHECK-LABEL: get_t2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $14
+  %1 = call i64 @llvm.read_register.i64(metadata !10)
+  ret i64 %1
+}
+
+define i64 @get_t3() {
+; CHECK-LABEL: get_t3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $15
+  %1 = call i64 @llvm.read_register.i64(metadata !11)
+  ret i64 %1
+}
+
+define i64 @get_t4() {
+; CHECK-LABEL: get_t4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $12
+  %1 = call i64 @llvm.read_register.i64(metadata !12)
+  ret i64 %1
+}
+
+define i64 @get_t5() {
+; CHECK-LABEL: get_t5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $13
+  %1 = call i64 @llvm.read_register.i64(metadata !13)
+  ret i64 %1
+}
+
+define i64 @get_t6() {
+; CHECK-LABEL: get_t6:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $14
+  %1 = call i64 @llvm.read_register.i64(metadata !14)
+  ret i64 %1
+}
+
+define i64 @get_t7() {
+; CHECK-LABEL: get_t7:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $15
+  %1 = call i64 @llvm.read_register.i64(metadata !15)
+  ret i64 %1
+}
+
+define i64 @get_s0() {
+; CHECK-LABEL: get_s0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $16
+  %1 = call i64 @llvm.read_register.i64(metadata !16)
+  ret i64 %1
+}
+
+define i64 @get_s1() {
+; CHECK-LABEL: get_s1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $17
+  %1 = call i64 @llvm.read_register.i64(metadata !17)
+  ret i64 %1
+}
+
+define i64 @get_s2() {
+; CHECK-LABEL: get_s2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $18
+  %1 = call i64 @llvm.read_register.i64(metadata !18)
+  ret i64 %1
+}
+
+define i64 @get_s3() {
+; CHECK-LABEL: get_s3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $19
+  %1 = call i64 @llvm.read_register.i64(metadata !19)
+  ret i64 %1
+}
+
+define i64 @get_s4() {
+; CHECK-LABEL: get_s4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $20
+  %1 = call i64 @llvm.read_register.i64(metadata !20)
+  ret i64 %1
+}
+
+define i64 @get_s5() {
+; CHECK-LABEL: get_s5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $21
+  %1 = call i64 @llvm.read_register.i64(metadata !21)
+  ret i64 %1
+}
+
+define i64 @get_s6() {
+; CHECK-LABEL: get_s6:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $22
+  %1 = call i64 @llvm.read_register.i64(metadata !22)
+  ret i64 %1
+}
+
+define i64 @get_s7() {
+; CHECK-LABEL: get_s7:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $23
+  %1 = call i64 @llvm.read_register.i64(metadata !23)
+  ret i64 %1
+}
+
+define i64 @get_t8() {
+; CHECK-LABEL: get_t8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $24
+  %1 = call i64 @llvm.read_register.i64(metadata !24)
+  ret i64 %1
+}
+
+define i64 @get_t9() {
+; CHECK-LABEL: get_t9:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $25
+  %1 = call i64 @llvm.read_register.i64(metadata !25)
+  ret i64 %1
+}
+
+define i64 @get_k0() {
+; CHECK-LABEL: get_k0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $26
+  %1 = call i64 @llvm.read_register.i64(metadata !26)
+  ret i64 %1
+}
+
+define i64 @get_k1() {
+; CHECK-LABEL: get_k1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $27
+  %1 = call i64 @llvm.read_register.i64(metadata !27)
+  ret i64 %1
+}
+
+define i64 @get_$gp() {
+; CHECK-LABEL: get_$gp:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    move $2, $gp
-  %1 = call i64 @llvm.read_register.i64(metadata !0)
+  %1 = call i64 @llvm.read_register.i64(metadata !28)
   ret i64 %1
 }
 
 define i64 @get_sp() {
 ; CHECK-LABEL: get_sp:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    jr $ra
 ; CHECK-NEXT:    move $2, $sp
-  %1 = call i64 @llvm.read_register.i64(metadata !1)
+  %1 = call i64 @llvm.read_register.i64(metadata !29)
+  ret i64 %1
+}
+
+define i64 @get_fp() {
+; CHECK-LABEL: get_fp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $fp
+  %1 = call i64 @llvm.read_register.i64(metadata !30)
+  ret i64 %1
+}
+
+define i64 @get_ra() {
+; CHECK-LABEL: get_ra:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $ra
+  %1 = call i64 @llvm.read_register.i64(metadata !31)
   ret i64 %1
 }
 
-!llvm.named.register.$28 = !{!0}
-!llvm.named.register.sp = !{!1}
+!llvm.named.register = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15, !16, !17, !18, !19, !20, !21, !22, !23, !24, !25, !26, !27, !28, !29, !30, !31}
 
-!0 = !{!"$28"}
-!1 = !{!"sp"}
+!0 = !{!"$zero"}
+!1 = !{!"$at"}
+!2 = !{!"$v0"}
+!3 = !{!"$v1"}
+!4 = !{!"$a0"}
+!5 = !{!"$a1"}
+!6 = !{!"$a2"}
+!7 = !{!"$a3"}
+!8 = !{!"$t0"}
+!9 = !{!"$t1"}
+!10 = !{!"$t2"}
+!11 = !{!"$t3"}
+!12 = !{!"$t4"}
+!13 = !{!"$t5"}
+!14 = !{!"$t6"}
+!15 = !{!"$t7"}
+!16 = !{!"$s0"}
+!17 = !{!"$s1"}
+!18 = !{!"$s2"}
+!19 = !{!"$s3"}
+!20 = !{!"$s4"}
+!21 = !{!"$s5"}
+!22 = !{!"$s6"}
+!23 = !{!"$s7"}
+!24 = !{!"$t8"}
+!25 = !{!"$t9"}
+!26 = !{!"$k0"}
+!27 = !{!"$k1"}
+!28 = !{!"$gp"}
+!29 = !{!"$sp"}
+!30 = !{!"$fp"}
+!31 = !{!"$ra"}
diff --git a/llvm/test/CodeGen/Mips/named-register-o32.ll b/llvm/test/CodeGen/Mips/named-register-o32.ll
index 280c56e4db6a4..a12f6662962e8 100644
--- a/llvm/test/CodeGen/Mips/named-register-o32.ll
+++ b/llvm/test/CodeGen/Mips/named-register-o32.ll
@@ -1,29 +1,296 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=mips -relocation-model=static -mattr=+noabicalls \
+; RUN: llc -mtriple=mips -relocation-model=static -O0 -mattr=+noabicalls \
 ; RUN:   < %s | FileCheck %s
 
-declare i32 @llvm.read_register.i32(metadata)
+declare i32 @llvm.read_register.i64(metadata)
 
-define i32 @get_gp() {
-; CHECK-LABEL: get_gp:
+define i32 @get_zero() {
+; CHECK-LABEL: get_zero:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $zero
+  %1 = call i32 @llvm.read_register.i32(metadata !0)
+  ret i32 %1
+}
+
+define i32 @get_at() {
+; CHECK-LABEL: get_at:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $2, $1
+  %1 = call i32 @llvm.read_register.i32(metadata !1)
+  ret i32 %1
+}
+
+define i32 @get_v0() {
+; CHECK-LABEL: get_v0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    jr $ra
+  %1 = call i32 @llvm.read_register.i32(metadata !2)
+  ret i32 %1
+}
+
+define i32 @get_v1() {
+; CHECK-LABEL: get_v1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $...
[truncated]

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@brad0 brad0 closed this Dec 9, 2025
@dyung dyung moved this from Needs Triage to Done in LLVM Release Status Dec 9, 2025
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