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[NFC][SPIRV] Fix breakage introduced by #170798 #171513

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Merged
AlexVlx merged 2 commits into from
Dec 9, 2025
Merged

[NFC][SPIRV] Fix breakage introduced by #170798 #171513

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c0933bf
i128 is legal in IR / MIR, even though it might yield a module which …
AlexVlx Dec 9, 2025
82dbfe9
Fix formatting.
AlexVlx Dec 9, 2025
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17 changes: 9 additions & 8 deletions llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -115,18 +115,19 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
v4s1, v4s8, v4s16, v4s32, v4s64};

auto allScalarsAndVectors = {
s1, s8, s16, s32, s64, v2s1, v2s8, v2s16, v2s32, v2s64,
v3s1, v3s8, v3s16, v3s32, v3s64, v4s1, v4s8, v4s16, v4s32, v4s64,
v8s1, v8s8, v8s16, v8s32, v8s64, v16s1, v16s8, v16s16, v16s32, v16s64};
s1, s8, s16, s32, s64, s128, v2s1, v2s8,
v2s16, v2s32, v2s64, v3s1, v3s8, v3s16, v3s32, v3s64,
v4s1, v4s8, v4s16, v4s32, v4s64, v8s1, v8s8, v8s16,
v8s32, v8s64, v16s1, v16s8, v16s16, v16s32, v16s64};

auto allIntScalarsAndVectors = {s8, s16, s32, s64, v2s8, v2s16,
v2s32, v2s64, v3s8, v3s16, v3s32, v3s64,
v4s8, v4s16, v4s32, v4s64, v8s8, v8s16,
v8s32, v8s64, v16s8, v16s16, v16s32, v16s64};
auto allIntScalarsAndVectors = {
s8, s16, s32, s64, s128, v2s8, v2s16, v2s32, v2s64,
v3s8, v3s16, v3s32, v3s64, v4s8, v4s16, v4s32, v4s64, v8s8,
v8s16, v8s32, v8s64, v16s8, v16s16, v16s32, v16s64};

auto allBoolScalarsAndVectors = {s1, v2s1, v3s1, v4s1, v8s1, v16s1};

auto allIntScalars = {s8, s16, s32, s64};
auto allIntScalars = {s8, s16, s32, s64, s128};

auto allFloatScalarsAndF16Vector2AndVector4s = {s16, s32, s64, v2s16, v4s16};

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4 changes: 2 additions & 2 deletions llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
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Expand Up @@ -388,11 +388,11 @@ static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR,

// To support current approach and limitations wrt. bit width here we widen a
// scalar register with a bit width greater than 1 to valid sizes and cap it to
// 64 width.
// 128 width.
static unsigned widenBitWidthToNextPow2(unsigned BitWidth) {
if (BitWidth == 1)
return 1; // No need to widen 1-bit values
return std::min(std::max(1u << Log2_32_Ceil(BitWidth), 8u), 64u);
return std::min(std::max(1u << Log2_32_Ceil(BitWidth), 8u), 128u);
}

static void widenScalarType(Register Reg, MachineRegisterInfo &MRI) {
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