[CIR][X86] Add support for alignd builtins #171621

YGGkk · 2025-12-10T13:57:16Z

No description provided.

github-actions · 2025-12-10T13:57:35Z

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llvmbot · 2025-12-10T13:58:05Z

@llvm/pr-subscribers-clang

Author: None (YGGkk)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/171621.diff

2 Files Affected:

(modified) clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp (+20-3)
(added) clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c (+55)

diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
index 62836ce0f7537..6b4e06966b828 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
@@ -1154,9 +1154,6 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
   case X86::BI__builtin_ia32_palignr128:
   case X86::BI__builtin_ia32_palignr256:
   case X86::BI__builtin_ia32_palignr512:
-  case X86::BI__builtin_ia32_alignd128:
-  case X86::BI__builtin_ia32_alignd256:
-  case X86::BI__builtin_ia32_alignd512:
   case X86::BI__builtin_ia32_alignq128:
   case X86::BI__builtin_ia32_alignq256:
   case X86::BI__builtin_ia32_alignq512:
@@ -1182,6 +1179,26 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
                  std::string("unimplemented X86 builtin call: ") +
                      getContext().BuiltinInfo.getName(builtinID));
     return {};
+  case X86::BI__builtin_ia32_alignd128:
+  case X86::BI__builtin_ia32_alignd256:
+  case X86::BI__builtin_ia32_alignd512: {
+    unsigned numElts = cast<cir::VectorType>(ops[0].getType()).getSize();
+    unsigned shiftVal =
+        ops[2].getDefiningOp<cir::ConstantOp>().getIntValue().getZExtValue() &
+        0xff;
+
+    // Mask the shift amount to width of a vector.
+    shiftVal &= numElts - 1;
+
+    SmallVector<mlir::Attribute, 16> indices;
+    mlir::Type i32Ty = builder.getSInt32Ty();
+    for (unsigned i = 0; i != numElts; ++i)
+      indices.push_back(
+          cir::IntAttr::get(i32Ty, i + shiftVal));
+
+    return builder.createVecShuffle(getLoc(expr->getExprLoc()), ops[0], ops[1],
+                                   indices);
+  }
   case X86::BI__builtin_ia32_kshiftliqi:
   case X86::BI__builtin_ia32_kshiftlihi:
   case X86::BI__builtin_ia32_kshiftlisi:
diff --git a/clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c
new file mode 100644
index 0000000000000..73c21d6f3d802
--- /dev/null
+++ b/clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c
@@ -0,0 +1,55 @@
+// RUN: %clang_cc1 -x c -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-cir -o %t.cir %s
+// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
+// RUN: %clang_cc1 -x c++ -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-cir -o %t.cir %s
+// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
+
+// RUN: %clang_cc1 -x c -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-llvm -o %t.ll %s
+// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s
+// RUN: %clang_cc1 -x c++ -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-llvm -o %t.ll %s
+// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s
+
+// RUN: %clang_cc1 -x c -ffreestanding -triple=x86_64-unknown-linux -target-feature +avx512vl -emit-llvm -Wall -Werror %s -o - | FileCheck %s -check-prefix=OGCG
+// RUN: %clang_cc1 -x c++ -ffreestanding -triple=x86_64-unknown-linux -target-feature +avx512vl -emit-llvm -Wall -Werror %s -o - | FileCheck %s -check-prefix=OGCG
+
+#include <immintrin.h>
+
+__v4si  test_builtin_ia32_alignd128()
+{
+  // CIR-LABEL: _builtin_ia32_alignd128
+  // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<4 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i] : !cir.vector<4 x !s32i>
+
+  // LLVM-LABEL: test_builtin_ia32_alignd128
+  // LLVM: shufflevector <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+
+  // OGCG-LABEL: test_builtin_ia32_alignd128
+  // OGCG: shufflevector <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  __v4si  vec1 = {0, 1, 2, 3};
+  __v4si  vec2 = {4, 5, 6, 7};
+  return __builtin_ia32_alignd128(vec1, vec2, 0);
+}
+
+__v8si  test_builtin_ia32_alignd256()
+{
+  // CIR-LABEL: _builtin_ia32_alignd256
+  // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<8 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i] : !cir.vector<8 x !s32i>
+  // LLVM-LABEL: test_builtin_ia32_alignd256
+  // LLVM: shufflevector <8 x i32> %{{.*}}, <8 x i32> %{{.*}}, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  // OGCG-LABEL: test_builtin_ia32_alignd256
+  // OGCG: shufflevector <8 x i32> %{{.*}}, <8 x i32> %{{.*}}, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  __v8si  vec1 = {0, 1, 2, 3, 4, 5, 6, 7};
+  __v8si  vec2 = {8, 9, 10, 11, 12, 13, 14, 15};
+  return __builtin_ia32_alignd256(vec1, vec2, 0);
+}
+
+__v16si  test_builtin_ia32_alignd512()
+{
+  // CIR-LABEL: _builtin_ia32_alignd512
+  // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<16 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i, #cir.int<8> : !s32i, #cir.int<9> : !s32i, #cir.int<10> : !s32i, #cir.int<11> : !s32i, #cir.int<12> : !s32i, #cir.int<13> : !s32i, #cir.int<14> : !s32i, #cir.int<15> : !s32i] : !cir.vector<16 x !s32i>
+  // LLVM-LABEL: test_builtin_ia32_alignd512
+  // LLVM: shufflevector <16 x i32> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  // OGCG-LABEL: test_builtin_ia32_alignd512
+  // OGCG: shufflevector <16 x i32> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  __v16si  vec1 = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
+  __v16si  vec2 = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31};
+  return __builtin_ia32_alignd512(vec1, vec2, 0);
+}
\ No newline at end of file

llvmbot · 2025-12-10T13:58:06Z

@llvm/pr-subscribers-clangir

Author: None (YGGkk)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/171621.diff

2 Files Affected:

(modified) clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp (+20-3)
(added) clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c (+55)

diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
index 62836ce0f7537..6b4e06966b828 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
@@ -1154,9 +1154,6 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
   case X86::BI__builtin_ia32_palignr128:
   case X86::BI__builtin_ia32_palignr256:
   case X86::BI__builtin_ia32_palignr512:
-  case X86::BI__builtin_ia32_alignd128:
-  case X86::BI__builtin_ia32_alignd256:
-  case X86::BI__builtin_ia32_alignd512:
   case X86::BI__builtin_ia32_alignq128:
   case X86::BI__builtin_ia32_alignq256:
   case X86::BI__builtin_ia32_alignq512:
@@ -1182,6 +1179,26 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
                  std::string("unimplemented X86 builtin call: ") +
                      getContext().BuiltinInfo.getName(builtinID));
     return {};
+  case X86::BI__builtin_ia32_alignd128:
+  case X86::BI__builtin_ia32_alignd256:
+  case X86::BI__builtin_ia32_alignd512: {
+    unsigned numElts = cast<cir::VectorType>(ops[0].getType()).getSize();
+    unsigned shiftVal =
+        ops[2].getDefiningOp<cir::ConstantOp>().getIntValue().getZExtValue() &
+        0xff;
+
+    // Mask the shift amount to width of a vector.
+    shiftVal &= numElts - 1;
+
+    SmallVector<mlir::Attribute, 16> indices;
+    mlir::Type i32Ty = builder.getSInt32Ty();
+    for (unsigned i = 0; i != numElts; ++i)
+      indices.push_back(
+          cir::IntAttr::get(i32Ty, i + shiftVal));
+
+    return builder.createVecShuffle(getLoc(expr->getExprLoc()), ops[0], ops[1],
+                                   indices);
+  }
   case X86::BI__builtin_ia32_kshiftliqi:
   case X86::BI__builtin_ia32_kshiftlihi:
   case X86::BI__builtin_ia32_kshiftlisi:
diff --git a/clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c
new file mode 100644
index 0000000000000..73c21d6f3d802
--- /dev/null
+++ b/clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c
@@ -0,0 +1,55 @@
+// RUN: %clang_cc1 -x c -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-cir -o %t.cir %s
+// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
+// RUN: %clang_cc1 -x c++ -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-cir -o %t.cir %s
+// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
+
+// RUN: %clang_cc1 -x c -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-llvm -o %t.ll %s
+// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s
+// RUN: %clang_cc1 -x c++ -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-llvm -o %t.ll %s
+// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s
+
+// RUN: %clang_cc1 -x c -ffreestanding -triple=x86_64-unknown-linux -target-feature +avx512vl -emit-llvm -Wall -Werror %s -o - | FileCheck %s -check-prefix=OGCG
+// RUN: %clang_cc1 -x c++ -ffreestanding -triple=x86_64-unknown-linux -target-feature +avx512vl -emit-llvm -Wall -Werror %s -o - | FileCheck %s -check-prefix=OGCG
+
+#include <immintrin.h>
+
+__v4si  test_builtin_ia32_alignd128()
+{
+  // CIR-LABEL: _builtin_ia32_alignd128
+  // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<4 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i] : !cir.vector<4 x !s32i>
+
+  // LLVM-LABEL: test_builtin_ia32_alignd128
+  // LLVM: shufflevector <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+
+  // OGCG-LABEL: test_builtin_ia32_alignd128
+  // OGCG: shufflevector <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  __v4si  vec1 = {0, 1, 2, 3};
+  __v4si  vec2 = {4, 5, 6, 7};
+  return __builtin_ia32_alignd128(vec1, vec2, 0);
+}
+
+__v8si  test_builtin_ia32_alignd256()
+{
+  // CIR-LABEL: _builtin_ia32_alignd256
+  // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<8 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i] : !cir.vector<8 x !s32i>
+  // LLVM-LABEL: test_builtin_ia32_alignd256
+  // LLVM: shufflevector <8 x i32> %{{.*}}, <8 x i32> %{{.*}}, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  // OGCG-LABEL: test_builtin_ia32_alignd256
+  // OGCG: shufflevector <8 x i32> %{{.*}}, <8 x i32> %{{.*}}, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  __v8si  vec1 = {0, 1, 2, 3, 4, 5, 6, 7};
+  __v8si  vec2 = {8, 9, 10, 11, 12, 13, 14, 15};
+  return __builtin_ia32_alignd256(vec1, vec2, 0);
+}
+
+__v16si  test_builtin_ia32_alignd512()
+{
+  // CIR-LABEL: _builtin_ia32_alignd512
+  // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<16 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i, #cir.int<8> : !s32i, #cir.int<9> : !s32i, #cir.int<10> : !s32i, #cir.int<11> : !s32i, #cir.int<12> : !s32i, #cir.int<13> : !s32i, #cir.int<14> : !s32i, #cir.int<15> : !s32i] : !cir.vector<16 x !s32i>
+  // LLVM-LABEL: test_builtin_ia32_alignd512
+  // LLVM: shufflevector <16 x i32> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  // OGCG-LABEL: test_builtin_ia32_alignd512
+  // OGCG: shufflevector <16 x i32> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  __v16si  vec1 = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
+  __v16si  vec2 = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31};
+  return __builtin_ia32_alignd512(vec1, vec2, 0);
+}
\ No newline at end of file

github-actions · 2025-12-10T14:47:45Z

🐧 Linux x64 Test Results

3047 tests passed
7 tests skipped

All executed tests passed, but another part of the build failed. Click on a failure below to see the details.

tools/clang/lib/CIR/CodeGen/CMakeFiles/obj.clangCIR.dir/CIRGenStmt.cpp.o

FAILED: tools/clang/lib/CIR/CodeGen/CMakeFiles/obj.clangCIR.dir/CIRGenStmt.cpp.o
sccache /opt/llvm/bin/clang++ -DCLANG_EXPORTS -DGTEST_HAS_RTTI=0 -D_DEBUG -D_GLIBCXX_ASSERTIONS -D_GLIBCXX_USE_CXX11_ABI=1 -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I/home/gha/actions-runner/_work/llvm-project/llvm-project/build/tools/clang/lib/CIR/CodeGen -I/home/gha/actions-runner/_work/llvm-project/llvm-project/clang/lib/CIR/CodeGen -I/home/gha/actions-runner/_work/llvm-project/llvm-project/clang/include -I/home/gha/actions-runner/_work/llvm-project/llvm-project/build/tools/clang/include -I/home/gha/actions-runner/_work/llvm-project/llvm-project/build/include -I/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/include -I/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/../mlir/include -I/home/gha/actions-runner/_work/llvm-project/llvm-project/build/tools/mlir/include -gmlt -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror -Werror=date-time -Werror=unguarded-availability-new -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic -Wno-long-long -Wc++98-compat-extra-semi -Wimplicit-fallthrough -Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wsuggest-override -Wstring-conversion -Wno-pass-failed -Wmisleading-indentation -Wctad-maybe-unsupported -fdiagnostics-color -ffunction-sections -fdata-sections -fno-common -Woverloaded-virtual -Wno-nested-anon-types -O3 -DNDEBUG -std=c++17  -fno-exceptions -funwind-tables -fno-rtti -UNDEBUG -MD -MT tools/clang/lib/CIR/CodeGen/CMakeFiles/obj.clangCIR.dir/CIRGenStmt.cpp.o -MF tools/clang/lib/CIR/CodeGen/CMakeFiles/obj.clangCIR.dir/CIRGenStmt.cpp.o.d -o tools/clang/lib/CIR/CodeGen/CMakeFiles/obj.clangCIR.dir/CIRGenStmt.cpp.o -c /home/gha/actions-runner/_work/llvm-project/llvm-project/clang/lib/CIR/CodeGen/CIRGenStmt.cpp
/home/gha/actions-runner/_work/llvm-project/llvm-project/clang/lib/CIR/CodeGen/CIRGenStmt.cpp:117:11: error: enumeration value 'DeferStmtClass' not handled in switch [-Werror,-Wswitch]
117 |   switch (s->getStmtClass()) {
|           ^~~~~~~~~~~~~~~~~
1 error generated.

If these failures are unrelated to your changes (for example tests are broken or flaky at HEAD), please open an issue at https://github.com/llvm/llvm-project/issues and add the infrastructure label.

YGGkk · 2025-12-10T15:25:18Z

part of #167765

andykaylor · 2025-12-10T17:51:33Z

clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp

  case X86::BI__builtin_ia32_alignq128:
  case X86::BI__builtin_ia32_alignq256:
  case X86::BI__builtin_ia32_alignq512:


These builtins should use the same implementation as the alignd builtins.

andykaylor · 2025-12-10T17:52:41Z

clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp

                 std::string("unimplemented X86 builtin call: ") +
                     getContext().BuiltinInfo.getName(builtinID));
    return {};
+  case X86::BI__builtin_ia32_alignd128:


Please do not change the order of the builtins in the switch. We've intentionally kept the same ordering as classic codegen to make it easier to navigate the code. Instead, duplicate the errorNYI handling above the builtins you are handling to prevent a fallthrough.

andykaylor · 2025-12-10T17:54:23Z

clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c

+  __v16si  vec1 = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
+  __v16si  vec2 = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31};
+  return __builtin_ia32_alignd512(vec1, vec2, 0);
+}


You are missing a line break at the end of this file.

andykaylor

lgtm

[CIR][X86] Add support for alignd builtins

b2a8864

YGGkk requested review from andykaylor, bcardosolopes, lanza and xlauko as code owners December 10, 2025 13:57

llvmbot added clang Clang issues not falling into any other category ClangIR Anything related to the ClangIR project labels Dec 10, 2025

YGGkk added 4 commits December 10, 2025 21:58

Merge branch 'main' into master

bbdf86f

[CIR][X86] Add support for alignd builtins

62df051

Merge branch 'master' of https://github.com/YGGkk/llvm-project

9a161c9

Merge branch 'main' into master

12e14dc

andykaylor reviewed Dec 10, 2025

View reviewed changes

YGGkk added 5 commits December 11, 2025 15:58

Merge branch 'llvm:main' into master

99adef3

[CIR][X86] Add support for align builtins

24d193b

Merge branch 'master' of https://github.com/YGGkk/llvm-project

893afab

Delete repeated alignd-builtins.c

af55858

fix some duplicate code

6fb0ad4

andykaylor approved these changes Dec 11, 2025

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YGGkk added 4 commits December 12, 2025 11:22

Merge branch 'main' into master

a4ec9dd

Merge branch 'main' into master

38d560c

Merge branch 'llvm:main' into master

e15a769

Merge branch 'main' into master

2fc3681

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[CIR][X86] Add support for alignd builtins #171621

[CIR][X86] Add support for alignd builtins #171621

YGGkk commented Dec 10, 2025

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github-actions bot commented Dec 10, 2025 •

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YGGkk commented Dec 10, 2025

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[CIR][X86] Add support for alignd builtins #171621

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[CIR][X86] Add support for alignd builtins #171621

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🐧 Linux x64 Test Results

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github-actions bot commented Dec 10, 2025 •

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