[RISCV] Add OperandType to tsimm5 used by Xsfvcp.

[topperc]

No description provided.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/171964.diff

1 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td (+2-1)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
index c07ed8596f009..bbc26a15e91a8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
@@ -37,7 +37,7 @@ def payload1 : PayloadOp<1>;
 def payload2 : PayloadOp<2>;
 def payload5 : PayloadOp<5>;
 
-def tsimm5 : Operand<XLenVT>, TImmLeaf<XLenVT, [{return isInt<5>(Imm);}]> {
+def tsimm5 : RISCVOp, TImmLeaf<XLenVT, [{return isInt<5>(Imm);}]> {
   let ParserMatchClass = SImmAsmOperand<5>;
   let EncoderMethod = "getImmOpValue";
   let DecoderMethod = "decodeSImmOperand<5>";
@@ -47,6 +47,7 @@ def tsimm5 : Operand<XLenVT>, TImmLeaf<XLenVT, [{return isInt<5>(Imm);}]> {
       return isInt<5>(Imm);
     return MCOp.isBareSymbolRef();
   }];
+  let OperandType = "OPERAND_SIMM5";
 }
 
 class SwapVCIXIns<dag funct6, dag rd, dag rs2, dag rs1, bit swap> {