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[msan] ability to make MSan up to 20x faster on AMD CPUs (-DLLVM_MSAN_SHADOW_OFFSET_2MB=1) #171993
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Is it possible to encode the change using only XorMask, without modifying ShadowBase?
When
ShadowBase == 0, the compiler is able to optimize it out. A non-zero shadow base requires an extra instruction for every shadow calculation e.g, https://github.com/llvm/llvm-project/pull/171993/files#diff-91f63a475808bb3cc923763edeb8a60749a879ea775ce1ebcc31af6c867f91e7:I suspect if the end addresses in kMemoryLayout were closed (e.g., 0x010000000000ULL - 1) instead of open, then it would be easy to do it entirely with XOR (though there might be other cleanup needed in MSan to handle closed end addresses).
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I don’t think this is something that can be resolved simply by using a closed end (i.e.
mem2shadow(end - 1)).If we directly embed kShadowOffset into the XOR mask, as follows:
Currently, kShadowOffset is 2 MiB, so this change would cause the lower 2 MiB and the upper 2 MiB within each 4 MiB shadow region to be swapped.
This may already be sufficient to mitigate the linear mapping issue (the mapping is linear within each 2 MiB region, but it is still NOT linear.
This kind of non-linearity would require special handling for every contiguous copy, which is quite tricky.
For example, with
memcpy(dst, src, n), we would no longer be able to directly apply the same operation to the shadow asmemcpy(mem2shadow(dst), mem2shadow(src), n), because the shadow corresponding tosrcmay not be the start of the shadow range for the entire[src, src + n)region.There was a problem hiding this comment.
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Also AFAICS it is free (or almost free), since the real asm looks like (with
-O3)Instead of
And I've also tested the performance on Intel, it looks the same - https://pastila.nl/?00b2e9d6/e11d914e0d9309f3444c4b244a9fa469#Ydv8nM20XBa2PJAPq+I6mQ==
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@Camsyn Thanks, good point!
@azat The machine code is longer if a non-zero immediate is needed:
Even if the CPU could execute both forms at the same speed, on the same execution ports, it is still increasing code size, icache pressure, etc.
Although it's probably not a huge impact, it would still be hard to justify making codegen worse for all x86 targets when the upside is only for a subset of Zen processors.
I do want MSan to work well for Zen as well, so how about a compile-time macro (when compiling MSan itself, not the target app) that enables the 2MB offset?
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I was also worrying about the overhead for other CPUs (since I've tested only few), so making it a compile time switch make sense.
Though it would be nice to have a test for this, but since it is compile time switch it will require separate job (and separate tests, at least one test maybe), what do you think about this?
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I mean I can make tests depends on this compile time switch, but unlikely this is desired, and one simple test will be sufficient for now