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[PowerPC] Add type checking for DMF insert 512 #172078

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[PowerPC] Add type checking for DMF insert 512 #172078

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b0fa349
Typecheck insert 512
RolandF77 Dec 12, 2025
d91a892
update tests
RolandF77 Dec 12, 2025
282f7c0
formatting
RolandF77 Dec 15, 2025
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38 changes: 16 additions & 22 deletions llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -11234,14 +11234,14 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
unsigned Opcode;
unsigned Subx;
if (HiLo == 0) {
Opcode = PPC::DMXXINSTDMR512;
Opcode = PPCISD::INST512;
Subx = PPC::sub_wacc_lo;
} else {
Opcode = PPC::DMXXINSTDMR512_HI;
Opcode = PPCISD::INST512HI;
Subx = PPC::sub_wacc_hi;
}
SDValue Ops[] = {Op.getOperand(2), Op.getOperand(3)};
SDValue Wacc = SDValue(DAG.getMachineNode(Opcode, dl, MVT::v512i1, Ops), 0);
SDValue Wacc = DAG.getNode(Opcode, dl, MVT::v512i1, Op.getOperand(2),
Op.getOperand(3));
SDValue SubReg = DAG.getTargetConstant(Subx, dl, MVT::i32);
return SDValue(DAG.getMachineNode(PPC::INSERT_SUBREG, dl, MVT::v1024i1,
Op.getOperand(1), Wacc, SubReg),
Expand Down Expand Up @@ -12012,13 +12012,11 @@ SDValue PPCTargetLowering::LowerDMFVectorLoad(SDValue Op,
}

SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
SDValue Lo(DAG.getMachineNode(PPC::DMXXINSTDMR512, dl, MVT::v512i1, Loads[0],
Loads[1]),
0);
SDValue Lo =
DAG.getNode(PPCISD::INST512, dl, MVT::v512i1, Loads[0], Loads[1]);
SDValue LoSub = DAG.getTargetConstant(PPC::sub_wacc_lo, dl, MVT::i32);
SDValue Hi(DAG.getMachineNode(PPC::DMXXINSTDMR512_HI, dl, MVT::v512i1,
Loads[2], Loads[3]),
0);
SDValue Hi =
DAG.getNode(PPCISD::INST512HI, dl, MVT::v512i1, Loads[2], Loads[3]);
SDValue HiSub = DAG.getTargetConstant(PPC::sub_wacc_hi, dl, MVT::i32);
SDValue RC = DAG.getTargetConstant(PPC::DMRRCRegClassID, dl, MVT::i32);
const SDValue Ops[] = {RC, Lo, LoSub, Hi, HiSub};
Expand All @@ -12032,12 +12030,10 @@ SDValue PPCTargetLowering::LowerDMFVectorLoad(SDValue Op,

// Handle Loads for V2048i1 which represents a dmr pair.
SDValue DmrPValue;
SDValue Dmr1Lo(DAG.getMachineNode(PPC::DMXXINSTDMR512, dl, MVT::v512i1,
Loads[4], Loads[5]),
0);
SDValue Dmr1Hi(DAG.getMachineNode(PPC::DMXXINSTDMR512_HI, dl, MVT::v512i1,
Loads[6], Loads[7]),
0);
SDValue Dmr1Lo =
DAG.getNode(PPCISD::INST512, dl, MVT::v512i1, Loads[4], Loads[5]);
SDValue Dmr1Hi =
DAG.getNode(PPCISD::INST512HI, dl, MVT::v512i1, Loads[6], Loads[7]);
const SDValue Dmr1Ops[] = {RC, Dmr1Lo, LoSub, Dmr1Hi, HiSub};
SDValue Dmr1Value = SDValue(
DAG.getMachineNode(PPC::REG_SEQUENCE, dl, MVT::v1024i1, Dmr1Ops), 0);
Expand All @@ -12057,13 +12053,11 @@ SDValue PPCTargetLowering::LowerDMFVectorLoad(SDValue Op,
SDValue PPCTargetLowering::DMFInsert1024(const SmallVectorImpl<SDValue> &Pairs,
const SDLoc &dl,
SelectionDAG &DAG) const {
SDValue Lo(DAG.getMachineNode(PPC::DMXXINSTDMR512, dl, MVT::v512i1, Pairs[0],
Pairs[1]),
0);
SDValue Lo =
DAG.getNode(PPCISD::INST512, dl, MVT::v512i1, Pairs[0], Pairs[1]);
SDValue LoSub = DAG.getTargetConstant(PPC::sub_wacc_lo, dl, MVT::i32);
SDValue Hi(DAG.getMachineNode(PPC::DMXXINSTDMR512_HI, dl, MVT::v512i1,
Pairs[2], Pairs[3]),
0);
SDValue Hi =
DAG.getNode(PPCISD::INST512HI, dl, MVT::v512i1, Pairs[2], Pairs[3]);
SDValue HiSub = DAG.getTargetConstant(PPC::sub_wacc_hi, dl, MVT::i32);
SDValue RC = DAG.getTargetConstant(PPC::DMRRCRegClassID, dl, MVT::i32);

Expand Down
25 changes: 23 additions & 2 deletions llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
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Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,23 @@
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// PowerPC ISA Future specific type constraints.
//

def SDT_PPCInst512 : SDTypeProfile<1, 2, [
SDTCisVT<0, v512i1>, SDTCisVT<1, v256i1>, SDTCisVT<2, v256i1>
]>;

//===----------------------------------------------------------------------===//
// ISA Future specific PPCISD nodes.
//

def PPCInst512 : SDNode<"PPCISD::INST512", SDT_PPCInst512, []>;
def PPCInst512Hi : SDNode<"PPCISD::INST512HI", SDT_PPCInst512, []>;

//===----------------------------------------------------------------------===//

class XX3Form_AT3_XABp5_P1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
string asmstr, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, NoItinerary> {
Expand Down Expand Up @@ -429,14 +446,18 @@ let Predicates = [MMA, IsISAFuture] in {
def DMXXINSTDMR512
: XX3Form_AT3_XABp5_P1<60, 234, (outs wacc:$AT),
(ins vsrprc:$XAp, vsrprc:$XBp),
"dmxxinstdmr512 $AT, $XAp, $XBp, 0", []> {
"dmxxinstdmr512 $AT, $XAp, $XBp, 0",
[(set v512i1:$AT, (PPCInst512 v256i1:$XAp,
v256i1:$XBp))]> {
let P = 0;
}

def DMXXINSTDMR512_HI
: XX3Form_AT3_XABp5_P1<60, 234, (outs wacc_hi:$AT),
(ins vsrprc:$XAp, vsrprc:$XBp),
"dmxxinstdmr512 $AT, $XAp, $XBp, 1", []> {
"dmxxinstdmr512 $AT, $XAp, $XBp, 1",
[(set v512i1:$AT, (PPCInst512Hi v256i1:$XAp,
v256i1:$XBp))]> {
let P = 1;
}

Expand Down
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