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Test assert zext #172138

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a80b806
[SDAG] fix miss opt: shl nuw + zext adds unnecessary masking
actinks Dec 12, 2025
dadbde1
fixup shl's promote, add trunc flags
actinks Dec 13, 2025
04ad587
test assert vs trunc flags
actinks Dec 13, 2025
e51edf3
update failed cases
actinks Dec 13, 2025
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20 changes: 16 additions & 4 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Expand Up @@ -1665,16 +1665,28 @@ SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
N0 = SExtPromoteOperand(N0, PVT);
else if (Opc == ISD::SRL)
N0 = ZExtPromoteOperand(N0, PVT);
else
N0 = PromoteOperand(N0, PVT, Replace);
else {
if (Op->getFlags().hasNoUnsignedWrap())
N0 = ZExtPromoteOperand(N0, PVT);
else if (Op->getFlags().hasNoSignedWrap())
N0 = SExtPromoteOperand(N0, PVT);
else
N0 = PromoteOperand(N0, PVT, Replace);
}

if (!N0.getNode())
return SDValue();

SDLoc DL(Op);
SDValue N1 = Op.getOperand(1);
SDValue RV =
DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, N0, N1));
SDValue POp = DAG.getNode(Opc, DL, PVT, N0, N1);
if (Opc == ISD::SRL ||
(Opc == ISD::SHL && Op->getFlags().hasNoUnsignedWrap()))
POp = DAG.getNode(ISD::AssertZext, DL, PVT, POp, DAG.getValueType(VT));
else if (Opc == ISD::SRA ||
(Opc == ISD::SHL && Op->getFlags().hasNoSignedWrap()))
POp = DAG.getNode(ISD::AssertSext, DL, PVT, POp, DAG.getValueType(VT));
SDValue RV = DAG.getNode(ISD::TRUNCATE, DL, VT, POp);

if (Replace)
ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
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3 changes: 3 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Expand Up @@ -1572,6 +1572,9 @@ SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) {
assert(VT.bitsLE(OpVT) && "Not extending!");
if (OpVT == VT)
return Op;
if (Op.getOpcode() == ISD::AssertZext &&
cast<VTSDNode>(Op.getOperand(1))->getVT().bitsLE(VT))
return Op;
APInt Imm = APInt::getLowBitsSet(OpVT.getScalarSizeInBits(),
VT.getScalarSizeInBits());
return getNode(ISD::AND, DL, OpVT, Op, getConstant(Imm, DL, OpVT));
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/2008-05-12-tailmerge-5.ll
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Expand Up @@ -34,14 +34,14 @@ define void @passing2(i64 %str.0, i64 %str.1, i16 signext %s, i32 %j, i8 signex
; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: shll $7, %eax
; CHECK-NEXT: cwtl
; CHECK-NEXT: shrl $7, %eax
; CHECK-NEXT: sarl $7, %eax
; CHECK-NEXT: cmpw {{[0-9]+}}(%rsp), %ax
; CHECK-NEXT: jne LBB0_6
; CHECK-NEXT: ## %bb.3: ## %bb51
; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: shll $7, %eax
; CHECK-NEXT: cwtl
; CHECK-NEXT: shrl $7, %eax
; CHECK-NEXT: sarl $7, %eax
; CHECK-NEXT: cmpw {{[0-9]+}}(%rsp), %ax
; CHECK-NEXT: jne LBB0_6
; CHECK-NEXT: ## %bb.4: ## %bb67
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44 changes: 21 additions & 23 deletions llvm/test/CodeGen/X86/andnot-patterns.ll
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Expand Up @@ -960,9 +960,9 @@ define i32 @andnot_bitreverse_i32(i32 %a0, i32 %a1) nounwind {
define i16 @andnot_bitreverse_i16(i16 %a0, i16 %a1) nounwind {
; X86-LABEL: andnot_bitreverse_i16:
; X86: # %bb.0:
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-NEXT: rolw $8, %ax
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: rolw $8, %cx
; X86-NEXT: movzwl %cx, %eax
; X86-NEXT: andl $3855, %ecx # imm = 0xF0F
; X86-NEXT: shll $4, %ecx
; X86-NEXT: shrl $4, %eax
Expand All @@ -985,19 +985,18 @@ define i16 @andnot_bitreverse_i16(i16 %a0, i16 %a1) nounwind {
;
; X64-NOBMI-LABEL: andnot_bitreverse_i16:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: # kill: def $esi killed $esi def $rsi
; X64-NOBMI-NEXT: rolw $8, %si
; X64-NOBMI-NEXT: movl %esi, %eax
; X64-NOBMI-NEXT: andl $3855, %eax # imm = 0xF0F
; X64-NOBMI-NEXT: shll $4, %eax
; X64-NOBMI-NEXT: shrl $4, %esi
; X64-NOBMI-NEXT: movzwl %si, %eax
; X64-NOBMI-NEXT: andl $3855, %esi # imm = 0xF0F
; X64-NOBMI-NEXT: orl %eax, %esi
; X64-NOBMI-NEXT: movl %esi, %eax
; X64-NOBMI-NEXT: shll $4, %esi
; X64-NOBMI-NEXT: shrl $4, %eax
; X64-NOBMI-NEXT: andl $3855, %eax # imm = 0xF0F
; X64-NOBMI-NEXT: orl %esi, %eax
; X64-NOBMI-NEXT: movl %eax, %ecx
; X64-NOBMI-NEXT: andl $13107, %ecx # imm = 0x3333
; X64-NOBMI-NEXT: shrl $2, %eax
; X64-NOBMI-NEXT: andl $13107, %eax # imm = 0x3333
; X64-NOBMI-NEXT: shrl $2, %esi
; X64-NOBMI-NEXT: andl $13107, %esi # imm = 0x3333
; X64-NOBMI-NEXT: leal (%rsi,%rax,4), %eax
; X64-NOBMI-NEXT: leal (%rax,%rcx,4), %eax
; X64-NOBMI-NEXT: movl %eax, %ecx
; X64-NOBMI-NEXT: andl $21845, %ecx # imm = 0x5555
; X64-NOBMI-NEXT: shrl %eax
Expand All @@ -1010,19 +1009,18 @@ define i16 @andnot_bitreverse_i16(i16 %a0, i16 %a1) nounwind {
;
; X64-BMI-LABEL: andnot_bitreverse_i16:
; X64-BMI: # %bb.0:
; X64-BMI-NEXT: # kill: def $esi killed $esi def $rsi
; X64-BMI-NEXT: rolw $8, %si
; X64-BMI-NEXT: movl %esi, %eax
; X64-BMI-NEXT: andl $3855, %eax # imm = 0xF0F
; X64-BMI-NEXT: shll $4, %eax
; X64-BMI-NEXT: shrl $4, %esi
; X64-BMI-NEXT: movzwl %si, %eax
; X64-BMI-NEXT: andl $3855, %esi # imm = 0xF0F
; X64-BMI-NEXT: orl %eax, %esi
; X64-BMI-NEXT: movl %esi, %eax
; X64-BMI-NEXT: shll $4, %esi
; X64-BMI-NEXT: shrl $4, %eax
; X64-BMI-NEXT: andl $3855, %eax # imm = 0xF0F
; X64-BMI-NEXT: orl %esi, %eax
; X64-BMI-NEXT: movl %eax, %ecx
; X64-BMI-NEXT: andl $13107, %ecx # imm = 0x3333
; X64-BMI-NEXT: shrl $2, %eax
; X64-BMI-NEXT: andl $13107, %eax # imm = 0x3333
; X64-BMI-NEXT: shrl $2, %esi
; X64-BMI-NEXT: andl $13107, %esi # imm = 0x3333
; X64-BMI-NEXT: leal (%rsi,%rax,4), %eax
; X64-BMI-NEXT: leal (%rax,%rcx,4), %eax
; X64-BMI-NEXT: movl %eax, %ecx
; X64-BMI-NEXT: andl $21845, %ecx # imm = 0x5555
; X64-BMI-NEXT: shrl %eax
Expand Down
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