[RISCV] Remove RISCVVMV0Elimination pass

[wangpc-pp]

• [RISCV] Remove RISCVVMV0Elimination pass
  This removes the use of RISCVVMV0Elimination pass.

• [RISCV] Add an artificial between copies of v0 and vmv0 users
  This fixes the only test with ran out of registers error.
  This avoids the overlap of v0 and fixes some correctness issues.

• [RISCV] Change the limit of register pressure VMV0 to 2
  Try to fix regressions.

• [RISCV] Change the limit of register pressure VMV0 to 1
  Try to fix regressions.

[wangpc-pp]

I am doing some attempts to fix some scheduling issues caused by v0 register and remove redundant vmv.v v0s , and I found the root cause is we still can't make vmv0 a safe register class to pass RA and scheduler. So I am trying to remove RISCVVMV0Elimination pass and finally let RA allocate it to v0.

We can pass the unit tests after this PR and we see some reductions of spill/reload/moves as well. I will try to make it pass the llvm-testsuite next week.

[lukel97]

I'm not sure if anythings changed in the RegisterCoalescer in the meantime, but do we still run into the issue where it will coalesce registers so instructions will have multiple operands in the vmv0 class? e.g. %x:vrnov0 = PseudoVADD_VV_M1_MASK %0:vrnov0, %1:vr, %2:vmv0, %3:vmv0, ...

[wangpc-pp]

I'm not sure if anythings changed in the RegisterCoalescer in the meantime, but do we still run into the issue where it will coalesce registers so instructions will have multiple operands in the vmv0 class? e.g. %x:vrnov0 = PseudoVADD_VV_M1_MASK %0:vrnov0, %1:vr, %2:vmv0, %3:vmv0, ...

I didn't change RegisterCoalescer, instead, I changed the operand register class used in VPseudoBinaryM and added a new scheduling mutation to avoid such cases. Now we can pass the llvm-testsuite.

[wangpc-pp]

Status updates:

1. We can pass llvm-testsuite after this PR so the correctness is not a noticeable concern now.
2. For the in-tree unit tests, we saw some improvements of removing vmvs but somehow there are several cases where we generate more spills/reloads. Overall the spilling issue is more significant than the gain.
3. We measured the dynamic instruction count of SPEC CPU 2017 and we didn't see big differences.

[wangpc-pp]

Regression.

[wangpc-pp]

Regression.

[wangpc-pp]

Regression.