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5 changes: 1 addition & 4 deletions mlir/include/mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h
Original file line number Diff line number Diff line change
Expand Up @@ -282,11 +282,8 @@ struct BMGuArch : public Xe2Plus {
inline const uArch *getUArch(llvm::StringRef archName) {
if (archName.equals_insensitive("pvc"))
return PVCuArch::getInstance();
else if (archName.equals_insensitive("bmg"))
if (archName.equals_insensitive("bmg"))
return BMGuArch::getInstance();
else
llvm_unreachable("No matching uArch found");

return nullptr;
}

Expand Down
44 changes: 33 additions & 11 deletions mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -576,7 +576,9 @@ void LayoutInfoPropagation::visitPrefetchNdOp(
// prefetch.
auto tdescTy = prefetch.getTensorDescType();

const auto *uArch = getUArch(getChipStr(prefetch).value_or(""));
const uArch *uArch = getUArch(getChipStr(prefetch).value_or(""));
if (!uArch)
return;
const auto *uArchInstruction =
dyn_cast<xegpu::uArch::Subgroup2DBlockPrefetchInstruction>(
uArch->getInstruction(
Expand Down Expand Up @@ -630,7 +632,9 @@ void LayoutInfoPropagation::visitVectorMultiReductionOp(
VectorType sourceTy = reduction.getSourceVectorType();
SmallVector<int64_t> reductionDims(reduction.getReductionDims());

const auto *uArch = getUArch(xegpu::getChipStr(reduction).value_or(""));
const uArch *uArch = getUArch(xegpu::getChipStr(reduction).value_or(""));
if (!uArch)
return;
auto consumerLayoutAttr =
dyn_cast<xegpu::DistributeLayoutAttr>(resLayoutInfo.get());

Expand Down Expand Up @@ -739,7 +743,9 @@ void LayoutInfoPropagation::visitDpasOp(
dpasBLayout = LayoutInfo(anchorLayoutB);
dpasCDLayout = LayoutInfo(anchorLayoutCD);
} else {
const auto *uArch = getUArch(getChipStr(dpas).value_or(""));
const uArch *uArch = getUArch(getChipStr(dpas).value_or(""));
if (!uArch)
return;
VectorType aTy = dpas.getLhsType();
VectorType bTy = dpas.getRhsType();
VectorType cdTy = dpas.getResultType();
Expand Down Expand Up @@ -795,7 +801,9 @@ void LayoutInfoPropagation::visitStoreNdOp(
if (hasParamsOfLayoutKind(anchorLayout)) {
storeLayout = LayoutInfo(anchorLayout);
} else {
const auto *uArch = getUArch(getChipStr(store).value_or(""));
const uArch *uArch = getUArch(getChipStr(store).value_or(""));
if (!uArch)
return;
const auto *uArchInstruction =
dyn_cast<xegpu::uArch::Subgroup2DBlockStoreInstruction>(
uArch->getInstruction(
Expand Down Expand Up @@ -924,7 +932,9 @@ void LayoutInfoPropagation::visitVectorBitcastOp(

auto consumerLayoutAttr =
dyn_cast<xegpu::DistributeLayoutAttr>(resLayoutInfo.get());
const auto *uArch = getUArch(xegpu::getChipStr(bitcast).value_or(""));
const uArch *uArch = getUArch(xegpu::getChipStr(bitcast).value_or(""));
if (!uArch)
return;
auto requiredResLayoutAttr = setupBitCastResultLayout(
layoutKind, srcVecType, resVecType, consumerLayoutAttr, uArch);

Expand Down Expand Up @@ -954,8 +964,10 @@ void LayoutInfoPropagation::visitInsertStridedSliceOp(

auto consumerLayoutAttr =
dyn_cast<xegpu::DistributeLayoutAttr>(resLayoutInfo.get());
const auto *uArch =
const uArch *uArch =
getUArch(xegpu::getChipStr(insertStridedSlice).value_or(""));
if (!uArch)
return;

auto requiredResLayoutAttr = xegpu::setupInsertStridedSliceResultLayout(
layoutKind, srcVecType, resVecType, consumerLayoutAttr, uArch);
Expand All @@ -978,7 +990,9 @@ void LayoutInfoPropagation::visitLoadGatherOp(
ArrayRef<const LayoutInfoLattice *> results) {
xegpu::DistributeLayoutAttr requiredAnchorLayoutAttr;
xegpu::DistributeLayoutAttr anchorLayoutAttr = load.getLayoutAttr();
const auto *uArch = getUArch(getChipStr(load).value_or(""));
const uArch *uArch = getUArch(getChipStr(load).value_or(""));
if (!uArch)
return;
auto subgroupSize = uArch->getSubgroupSize();
VectorType resVecTy = load.getValueType();
int chunkSize = load.getChunkSize().value_or(1);
Expand Down Expand Up @@ -1037,7 +1051,9 @@ void LayoutInfoPropagation::visitCreateDescOp(
// Need the layout of the descriptor to propagate to the operands.
if (!descLayout.isAssigned())
return;
const auto *uArch = getUArch(getChipStr(createDesc).value_or(""));
const uArch *uArch = getUArch(getChipStr(createDesc).value_or(""));
if (!uArch)
return;
// For offset operand propagate 1D default layout.
LayoutInfo layout = getDefaultSIMTLayoutInfo(createDesc->getContext(), 1,
uArch->getSubgroupSize());
Expand All @@ -1052,7 +1068,9 @@ void LayoutInfoPropagation::visitStoreScatterOp(

xegpu::DistributeLayoutAttr requiredAnchorLayoutAttr;
xegpu::DistributeLayoutAttr anchorLayoutAttr = storeScatter.getLayoutAttr();
const auto *uArch = getUArch(getChipStr(storeScatter).value_or(""));
const uArch *uArch = getUArch(getChipStr(storeScatter).value_or(""));
if (!uArch)
return;
auto subgroupSize = uArch->getSubgroupSize();
VectorType srcVecTy = storeScatter.getValueType();
int chunkSize = storeScatter.getChunkSize().value_or(1);
Expand Down Expand Up @@ -1117,7 +1135,9 @@ void LayoutInfoPropagation::visitLoadMatrixOp(
VectorType resVecTy =
llvm::cast<VectorType>(loadMatrixOp.getRes().getType());
assert(resVecTy.getRank() == 2 && "Expecting 2D vector for store matrix.");
const auto *uArch = getUArch(getChipStr(loadMatrixOp).value_or(""));
const uArch *uArch = getUArch(getChipStr(loadMatrixOp).value_or(""));
if (!uArch)
return;
auto requiredAnchorLayoutAttr = xegpu::setupLoadMatrixAnchorLayout(
layoutKind, resVecTy, consumerLayoutAttr, uArch);
loadMatrixOp.setLayoutAttr(requiredAnchorLayoutAttr);
Expand All @@ -1136,7 +1156,9 @@ void LayoutInfoPropagation::visitStoreMatrixOp(
VectorType srcVecTy =
llvm::cast<VectorType>(storeMatrix.getData().getType());
assert(srcVecTy.getRank() == 2 && "Expecting 2D vector for store matrix.");
const auto *uArch = getUArch(getChipStr(storeMatrix).value_or(""));
const uArch *uArch = getUArch(getChipStr(storeMatrix).value_or(""));
if (!uArch)
return;
auto requiredAnchorLayoutAttr =
xegpu::setupStoreMatrixAnchorLayout(layoutKind, srcVecTy, uArch);
storeMatrix.setLayoutAttr(requiredAnchorLayoutAttr);
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -522,7 +522,7 @@ struct SgToWiVectorReduction : public OpConversionPattern<vector::ReductionOp> {

// Get the subgroup size from the layout.
int64_t sgSize = layout.getEffectiveLaneLayoutAsInt()[0];
const auto *uArch = getUArch(xegpu::getChipStr(op).value_or(""));
const uArch *uArch = getUArch(xegpu::getChipStr(op).value_or(""));
if (!uArch)
return rewriter.notifyMatchFailure(
op, "xegpu::ReductionOp require target attribute attached to "
Expand Down
12 changes: 12 additions & 0 deletions mlir/test/Dialect/XeGPU/xegpu-subgroup-distribute-no-arch.mlir
Original file line number Diff line number Diff line change
@@ -0,0 +1,12 @@
// RUN: mlir-opt --xegpu-subgroup-distribute -split-input-file %s | FileCheck %s
// Regression test for https://github.com/llvm/llvm-project/issues/181531:
// Running --xegpu-subgroup-distribute without a chip target attribute used to
// call llvm_unreachable in getUArch(). The pass should now bail out gracefully.

// CHECK-LABEL: gpu.func @no_crash_without_chip_attr
// CHECK: gpu.return
gpu.module @test_module {
gpu.func @no_crash_without_chip_attr(%arg0: memref<8x16xf16>, %arg1: memref<8x16xf16>) {
gpu.return
}
}