[rtl] Split data and ECC of the register file

Until now, a single instance of the register file containing 32-bit
data words and 7-bit ECC tags was used. While the input of the
register file was driven by the main core, the output of the
register file was distributed to the main and the shadow core.

In this commit, we are splitting up the data and ECC parts into two
different register file instances:
 - (1) This instance is driven by the main core and only operates on
       the 32-bit data words. The outputs (32-bit data words) are
       forwarded to the main and the shadow core.
 - (2) This instance is driven by the shadow core and only operates
       on the 7-bit ECC words. The 7-bit ECC output is combined with
       the delayed 32-bit data output of the (1) RF instance. The
       shadow core uses ECC checkers to check if data and ECC (a)
       match and (b) are not manipulated using FI.

This helps us to save around 6 kGE of area.

Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>

Author: nasahlpa

doc/03_reference/coverage_plan.rst

@@ -338,6 +338,8 @@ For more detail about each security countermeasure in Ibex see :ref:`security`
 
 * ``cp_lockstep_err`` - Lockstep glitch fault seen.
 
+* ``cp_rf_glitch_err`` - Register file fault seen.
+
 * ``cp_pc_mismatch_err`` - PC mismatch error seen.
 
 The :ref:`security features Ibex implements <security>` are given specific security countermeasure names in OpenTitan (see 'Security Countermeasures' in the `Comportability Definition and Specification <https://opentitan.org/book/doc/contributing/hw/comportability/index.html#security-countermeasures>`_ documentation section).
@@ -358,6 +360,8 @@ The mapping between security countermeasures and coverpoints that demonstrate it
 +--------------------------------+-------------------------------------------------------+
 | DATA_REG_SW.INTEGRITY          | ``cp_rf_a_ecc_err`` ``cp_rf_b_ecc_err``               |
 +--------------------------------+-------------------------------------------------------+
+| DATA_REG_SW.GLITCH_DETECT      | ``cp_rf_glitch_err``                                  |
++--------------------------------+-------------------------------------------------------+
 | LOGIC.SHADOW                   | ``cp_lockstep_err``                                   |
 +--------------------------------+-------------------------------------------------------+
 | FETCH.CTRL.LC_GATED            | ``cp_fetch_enable``                                   |

doc/03_reference/verification_stages.rst

@@ -163,6 +163,8 @@ The mapping between countermeasures and tests is given below
 +--------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 | DATA_REG_SW.INTEGRITY          | ``riscv_rf_intg_test`` in Ibex DV.                                                                                                                                                                                                                                                                         |
 +--------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| DATA_REG_SW.GLITCH_DETECT      | Covered by formal verification of security countermeasures within OpenTitan.                                                                                                                                                                                                                               |
++--------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 | LOGIC.SHADOW                   | ``chip_sw_rv_core_ibex_lockstep_glitch`` top-level test in OpenTitan                                                                                                                                                                                                                                       |
 +--------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 | FETCH.CTRL.LC_GATED            | ``riscv_rand_instr_test`` in Ibex DV.                                                                                                                                                                                                                                                                      |

dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv

@@ -395,6 +395,7 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
     id_stall_type_last_valid;
 
   // V2S Related Probes for Top-Level
+  logic rf_glitch_err;
   logic lockstep_glitch_err;
 
   logic imem_single_cycle_response, dmem_single_cycle_response;
@@ -492,6 +493,7 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
     `DV_FCOV_EXPR_SEEN(mem_store_ecc_err, load_store_unit_i.store_resp_intg_err_o)
 
     `DV_FCOV_EXPR_SEEN(lockstep_err, lockstep_glitch_err)
+    `DV_FCOV_EXPR_SEEN(rf_glitch_err, rf_glitch_err)
     `DV_FCOV_EXPR_SEEN(pc_mismatch_err, if_stage_i.pc_mismatch_alert_o)
 
     cp_fetch_enable: coverpoint fetch_enable_i {

dv/uvm/core_ibex/tb/core_ibex_tb_top.sv

@@ -198,6 +198,8 @@ module core_ibex_tb_top;
   end
 
 `ifndef DV_FCOV_DISABLE
+  assign dut.u_ibex_top.u_ibex_core.u_fcov_bind.rf_glitch_err =
+    dut.u_ibex_top.alert_major_internal_o;
   assign dut.u_ibex_top.u_ibex_core.u_fcov_bind.lockstep_glitch_err =
     dut.u_ibex_top.lockstep_alert_major_internal;
 `endif