[rtl] Improve FI hardening around data_rvalid_i #1968
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Previously, it was possible to glitch data_rvalid_i at the interconnect level and if the data integrity bits happened to be valid, Ibex would write the current data_rdata_i into the register file even if it wasn't doing a load. Since the glitch is inserted at the interconnect level, both the main and the shadow core are affected equally. This commit changes the WB stage to only forward the LSU write enable, which is generated from data_rvalid_i, when Ibex is actually waiting for an interconnect response for a load instruction. This substantially narrows down the window for attacks at the interconnect level. Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
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Very good catch!
Do we also need to harden the Ibex configuration without WB stage against this? (Probably not for OT, but we could create an issue in the Ibex repo to track this?)
Thanks @andreaskurth . I think I wouldn't harden the configuration without WB, as this config is less relevant and the hardening there would be more involved. The nice thing about hardening the WB configuration is that the required flop is already there. So it's just about adding a single AND gate. |
Thanks for the explanation. I agree that hardening the config without WB is not necessary at the moment, but I would suggest to either track this as an issue or document that some hardening requires the WB stage to be instantiated. Right now, the Ibex docs state "Ibex implements a set of extra features (when the |
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This sounds reasonable @andreaskurth . I've created an issue to track this here #1970 and will now merge this PR. |
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Previously, it was possible to glitch data_rvalid_i at the interconnect level and if the data integrity bits happened to be valid, Ibex would write the current data_rdata_i into the register file even if it wasn't doing a load. Since the glitch is inserted at the interconnect level, both the main and the shadow core are affected equally.
This commit changes the WB stage to only forward the LSU write enable, which is generated from data_rvalid_i, when Ibex is actually waiting for an interconnect response for a load instruction. This substantially narrows down the window for attacks at the interconnect level.