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[ot] hw/riscv: ot_earlgrey: assign an identifier to each UART #118

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Merged
merged 2 commits into from
Jan 27, 2025
Merged

[ot] hw/riscv: ot_earlgrey: assign an identifier to each UART #118

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31b8cd2
[ot] hw/opentitan: ot_uart: add ot_id identifier string
rivos-eblot Jan 23, 2025
728a38d
[ot] hw/riscv: ot_earlgrey: assign an identifier to each UART
rivos-eblot Jan 23, 2025
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38 changes: 23 additions & 15 deletions hw/opentitan/ot_uart.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,7 @@
* QEMU OpenTitan UART device
*
* Copyright (c) 2022-2024 Rivos, Inc.
* Copyright (c) 2025 lowRISC contributors.
*
* Author(s):
* Loïc Lefort <loic@rivosinc.com>
Expand Down Expand Up @@ -156,6 +157,7 @@ struct OtUARTState {
uint32_t tx_watermark_level;
guint watch_tag;

char *ot_id;
uint32_t pclk;
CharBackend chr;
};
Expand All @@ -180,7 +182,7 @@ static void ot_uart_update_irqs(OtUARTState *s)
{
uint32_t state_masked = s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE];

trace_ot_uart_irqs(s->regs[R_INTR_STATE], s->regs[R_INTR_ENABLE],
trace_ot_uart_irqs(s->ot_id, s->regs[R_INTR_STATE], s->regs[R_INTR_ENABLE],
state_masked);

for (int index = 0; index < OT_UART_IRQ_NUM; index++) {
Expand Down Expand Up @@ -451,7 +453,7 @@ static uint64_t ot_uart_read(void *opaque, hwaddr addr, unsigned size)
}

uint32_t pc = ibex_get_current_pc();
trace_ot_uart_io_read_out((uint32_t)addr, REG_NAME(reg), val32, pc);
trace_ot_uart_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32, pc);

return (uint64_t)val32;
}
Expand All @@ -466,7 +468,7 @@ static void ot_uart_write(void *opaque, hwaddr addr, uint64_t val64,
hwaddr reg = R32_OFF(addr);

uint32_t pc = ibex_get_current_pc();
trace_ot_uart_io_write((uint32_t)addr, REG_NAME(reg), val32, pc);
trace_ot_uart_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32, pc);

switch (reg) {
case R_INTR_STATE:
Expand Down Expand Up @@ -557,6 +559,7 @@ static const MemoryRegionOps ot_uart_ops = {
};

static Property ot_uart_properties[] = {
DEFINE_PROP_STRING("ot_id", OtUARTState, ot_id),
DEFINE_PROP_CHR("chardev", OtUARTState, chr),
DEFINE_PROP_UINT32("pclk", OtUARTState, pclk, 0u),
DEFINE_PROP_END_OF_LIST(),
Expand All @@ -579,18 +582,6 @@ static int ot_uart_be_change(void *opaque)
return 0;
}

static void ot_uart_realize(DeviceState *dev, Error **errp)
{
OtUARTState *s = OT_UART(dev);
(void)errp;

fifo8_create(&s->tx_fifo, OT_UART_TX_FIFO_SIZE);
fifo8_create(&s->rx_fifo, OT_UART_RX_FIFO_SIZE);

qemu_chr_fe_set_handlers(&s->chr, ot_uart_can_receive, ot_uart_receive,
NULL, ot_uart_be_change, s, NULL, true);
}

static void ot_uart_reset(DeviceState *dev)
{
OtUARTState *s = OT_UART(dev);
Expand All @@ -608,6 +599,23 @@ static void ot_uart_reset(DeviceState *dev)
ibex_irq_set(&s->alert, 0);
}

static void ot_uart_realize(DeviceState *dev, Error **errp)
{
OtUARTState *s = OT_UART(dev);
(void)errp;

if (!s->ot_id) {
s->ot_id =
g_strdup(object_get_canonical_path_component(OBJECT(s)->parent));
}

fifo8_create(&s->tx_fifo, OT_UART_TX_FIFO_SIZE);
fifo8_create(&s->rx_fifo, OT_UART_RX_FIFO_SIZE);

qemu_chr_fe_set_handlers(&s->chr, ot_uart_can_receive, ot_uart_receive,
NULL, ot_uart_be_change, s, NULL, true);
}

static void ot_uart_init(Object *obj)
{
OtUARTState *s = OT_UART(obj);
Expand Down
8 changes: 4 additions & 4 deletions hw/opentitan/trace-events
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Expand Up @@ -503,7 +503,7 @@ ot_timer_update_irq(const char *id, bool level) "%s: %d"

# ot_uart.c

ot_uart_debug(const char *msg) "%s"
ot_uart_io_read_out(uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "addr=0x%02x (%s), val=0x%x, pc=0x%x"
ot_uart_io_write(uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "addr=0x%02x (%s), val=0x%x, pc=0x%x"
ot_uart_irqs(uint32_t active, uint32_t mask, uint32_t eff) "act:0x%08x msk:0x%08x eff:0x%08x"
ot_uart_debug(const char *id, const char *msg) "%s: %s"
ot_uart_io_read_out(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
ot_uart_io_write(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
ot_uart_irqs(const char *id, uint32_t active, uint32_t mask, uint32_t eff) "%s: act:0x%08x msk:0x%08x eff:0x%08x"
4 changes: 4 additions & 0 deletions hw/riscv/ot_earlgrey.c
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Expand Up @@ -353,6 +353,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
OT_EG_SOC_GPIO_ALERT(0, 0)
),
.prop = IBEXDEVICEPROPDEFS(
IBEX_DEV_STRING_PROP("ot_id", "u0"),
IBEX_DEV_UINT_PROP("pclk", OT_EG_PERIPHERAL_CLK_HZ)
),
},
Expand All @@ -376,6 +377,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
OT_EG_SOC_GPIO_ALERT(0, 1)
),
.prop = IBEXDEVICEPROPDEFS(
IBEX_DEV_STRING_PROP("ot_id", "u1"),
IBEX_DEV_UINT_PROP("pclk", OT_EG_PERIPHERAL_CLK_HZ)
),
},
Expand All @@ -399,6 +401,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
OT_EG_SOC_GPIO_ALERT(0, 2)
),
.prop = IBEXDEVICEPROPDEFS(
IBEX_DEV_STRING_PROP("ot_id", "u2"),
IBEX_DEV_UINT_PROP("pclk", OT_EG_PERIPHERAL_CLK_HZ)
),
},
Expand All @@ -422,6 +425,7 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
OT_EG_SOC_GPIO_ALERT(0, 3)
),
.prop = IBEXDEVICEPROPDEFS(
IBEX_DEV_STRING_PROP("ot_id", "u3"),
IBEX_DEV_UINT_PROP("pclk", OT_EG_PERIPHERAL_CLK_HZ)
),
},
Expand Down
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