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[ot] hw/opentitan: ot_spi_host: rework SPI Host #139
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Merged
rivos-eblot
merged 23 commits into
lowRISC:ot-earlgrey-9.2.0
from
rivos-eblot:dev/ebl/spihost_active_bit
Feb 13, 2025
Merged
[ot] hw/opentitan: ot_spi_host: rework SPI Host #139
rivos-eblot
merged 23 commits into
lowRISC:ot-earlgrey-9.2.0
from
rivos-eblot:dev/ebl/spihost_active_bit
Feb 13, 2025
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…ages Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
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loiclefort
reviewed
Feb 11, 2025
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Ideally, this should be implemented as a irq signal to receive dynamic clock settings from the clock manager. Until ot_clkmgr supports this feature, use a simple property. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
…ation Restore configuration that got unexpectedly discarded in "rework SPI event management" commit Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Documentation was misleading: "the command is complete when STATUS.ACTIVE goes low." It turns out STATUS.active goes low when the last pushed command is completed, in other words, STATUS.active is not released as soon as a command is complete. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Update SPI Host doc clarifies that registers are -not- reset upon a SW reset. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
…ecated Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Observing Verilator waves, it seems nothing precludes the SPI HOST FSM from executing on error. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Observing Verilator waves, the command FIFO only contains next command, not the one that is being executed. In other words, there can be 5 in-fly commands, not 4, as 4 are stored in the command FIFO + 1 is being executed. Remove CS channel limitation (from 8 to 32 bits) and command tracking value (from 16 to 32 bits) Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Active command status provides the same information. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
…ce_status Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Command completion is handled in a dedicated function. Add a short delay on command push to yield execution back to the vCPU before kicking the FSM. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
…mand Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
… I/F Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Remove deprecated Doxygen-like C comments, use QEMU style. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
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loiclefort
approved these changes
Feb 11, 2025
When overriding the parent's reset implementation, the child is responsible to call its parent's implementation. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
OT_SPI_HOST_IRQ_NUM is no longer used. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
…tion Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
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loiclefort
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Feb 12, 2025
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All SPI Host tests from
sw/device/tests
now passSee #129 for details.