Update QEMU implementation #157
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loiclefort
commented
Jul 22, 2025
loiclefort
commented
- Add initial support for dynamic clock management (clocks can be modified at runtime rather than build time). Clock tree follows OpenTitan HW: AST --> Clock Manager --> Devices. Clock gating/hinting is not yet supported
- Improve LC controller implementation
- Add code execution disablement
- Darjeeling KeyManager DPE with AES/KMAC/OTBN sideloading
- Bug fixing
…ettable API Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Use the PMP implementation from v9.2.0 Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
When running in TOR mode (Top of Range) the next PMP entry controls whether the entry is locked. However simply checking if the PMP_LOCK bit is set is not sufficient with the Smepmp extension which now provides a bit (mseccfg.RLB (Rule Lock Bypass)) to disregard the lock bits. In order to respect this bit use the convenience pmp_is_locked() function rather than directly checking PMP_LOCK since this function checks mseccfg.RLB. Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
When Smepmp is supported, mseccfg.RLB allows bypassing locks when writing CSRs but should not affect interpretation of actual PMP rules. This is not the case with the current implementation where pmp_hart_has_privs calls pmp_is_locked which implements mseccfg.RLB bypass. This commit implements the correct behavior by removing mseccfg.RLB bypass from pmp_is_locked. RLB bypass when writing CSRs is implemented by adding a new pmp_is_readonly function that calls pmp_is_locked and check mseccfg.RLB. pmp_write_cfg and pmpaddr_csr_write are changed to use this new function. Signed-off-by: Loïc Lefort <loic@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20250313193011.720075-2-loic@rivosinc.com>
…function Signed-off-by: Loïc Lefort <loic@rivosinc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20250313193011.720075-3-loic@rivosinc.com>
… MML mode With Machine Mode Lockdown (mseccfg.MML) set and RLB not set, checks on pmpcfg writes would match the wrong cases of Smepmp truth table. The existing code allows writes for the following cases: - L=1, X=0: cases 8, 10, 12, 14 - L=0, RWX!=WX: cases 0-2, 4-6 This leaves cases 3, 7, 9, 11, 13, 15 for which writes are ignored. From the Smepmp specification: "Adding a rule with executable privileges that either is M-mode-only or a locked Shared-Region is not possible (...)" This description matches cases 9-11, 13 of the truth table. This commit implements an explicit check for these cases by using pmp_get_epmp_operation to convert between PMP configuration and Smepmp truth table cases. Signed-off-by: Loïc Lefort <loic@rivosinc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20250313193011.720075-4-loic@rivosinc.com>
…hanged Signed-off-by: Loïc Lefort <loic@rivosinc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20250313193011.720075-5-loic@rivosinc.com>
Remove useless check in pmp_is_locked, the function will return 0 in either case. Signed-off-by: Loïc Lefort <loic@rivosinc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20250313193011.720075-6-loic@rivosinc.com>
- re-organize code to follow the common function order for all OT devices - prepare for clock management upgrade Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
…ions Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
…tions Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Some devices may disable instruction fetch while keeping data access. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
If no OTP file is in use, default to enabling execution from SRAM. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
…t to ot_vmapper Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Instruction fetch management is handled with ot_vmapper. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
…nt to ot_vmapper Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Instruction fetch management is handled with ot_vmapper. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
…out of spec. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
* EG_252 matches EarlGrey 2.5.2-rc0, which is the first supported version of QEMU OpenTitan emulation * DJ_PRE is the initial Darjeeling version based on EarlGrey 2.5.2-rc0 Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
* EG_252 matches EarlGrey 2.5.2-rc0, which is the first supported version of QEMU OpenTitan emulation * DJ_PRE is the initial Darjeeling version based on EarlGrey 2.5.2-rc0 Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
…ontrol warning Some SRAM controller may never be associated with an ot_vmapper, leading to recurrent warnings. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
use-after-free issue. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
With multiple Debug Module, it is sometimes useful to track down where DTM requests are routed to. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Address a misunderstanding in RISC-V debug spec 0.13.2: DMCONTROL.dmactive bit should not be automatically reverted back to 1 once is reset is completed: it seems it is up to the remote debugger to release the DM from the reset state, which is now implemented as such. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
…dress for debug/trace purposes Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Loïc Lefort <loic@rivosinc.com>
Signed-off-by: Loïc Lefort <loic@rivosinc.com>
Signed-off-by: Loïc Lefort <loic@rivosinc.com>
Signed-off-by: Loïc Lefort <loic@rivosinc.com>
Signed-off-by: Loïc Lefort <loic@rivosinc.com>
…type Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
…type Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
…methods These should enable providing data extraction method to other modules. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
…ation Not yet fully tested. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
…led image files Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
It should be used to report an invalid parsed argument, to delegate ArgumentParser validation to modules. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
…o a file Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
…ace event name Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
… a single test When define as a test option, the VCP port are also logged into an additional file. It is possible to use a temporary file to perform post-analysis of the UART outputs Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
…r DPE testing Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Loïc Lefort <loic@rivosinc.com>
Signed-off-by: Loïc Lefort <loic@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Loïc Lefort <loic@rivosinc.com>
Allow commit line to start with "FROMLIST:" to indicate a commit cherry-picked from a mailing list. Signed-off-by: Loïc Lefort <loic@rivosinc.com>
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