earlgrey, darjeeling: rework machine reset management

[rivos-eblot]

Rework machine reset management, including board and SoC:

1. Earlgrey and Darjeeling machine implement reset the same way, to ease maintenance
2. Simplify overall reset management, with some better defined exceptions:
   • CPU/hart which does not leave reset automatically, so that power manager fetch enable signal triggers CPU execution to mimic real HW
   • SoC reset exit triggers ROM(s) loading, which in turn trigger power management state machine
3. Only rely on Resettable APIs to manage reset, remove all legacy reset APIs

[jwnrt]

LGTM. I tested resetting Earlgrey via the monitor and it works great now, thank you!

[loiclefort]

Spotted some stuff in comments otherwise LGTM

[loiclefort]

LGTM but it seems to be breaking some EG tests

[AlexJones0]

Thanks for looking into this! I feel like I lack the full understanding of QEMU's reset sequence to give a thorough review, but the changes seem sensible and well-documented, and all existing passing Earlgrey tests remain passing.

[AlexJones0]

LGTM but it seems to be breaking some EG tests

The CI failure is likely my fault - I merged a new test in upstream OpenTitan earlgrey_1.0.0 to do some basic testing of I2C in CI but didn't make a PR to update QEMU accordingly. Feel free to add the //sw/device/tests/qemu:i2c_qemu_test_sim_qemu_rom_with_fake_keys to scripts/opentitan/tests-passing.txt, or alternatively just merge this regardless of CI and I can PR a fix tomorrow.

@jwnrt I wonder if we should make passing tests (not marked as passing) non-failing in CI but give a loud warning, because otherwise CI is fragile to changes in earlgrey_1.0.0. Ideally that branch is taped-out so not much is changing but that may not be the case...

[jwnrt]

Yes, that sounds sensible. In any case this PR didn’t cause any problems so it looks okay to merge