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@rivos-eblot rivos-eblot commented Oct 16, 2025

  1. several constants and bitfields were still hardcoded for a specific top (likely EarlGrey)
  2. replace some constants with top-dependent macros
  3. implement initial support for clock domain crossing:
    several register properties are not used as-is, as they drive features implemented in the slow clock domain, while the registers themselves are in the default, "fast" clock domain. It is required for the guest SW to write and poll the CFG_CDC_SYNC register to commit new settings to the slow clock domain. QEMU was not supporting this feature, the
    guest SW could then miss to synchronize these features. Application was running fine on QEMU but not on the real HW. Note that the doc is out-of-date, and only the RTL can provide a list of the actual slow clock domain features gated by the CFG_CDC_DOMAIN. Update the guest error message to give a hint when reset cannot be successfully enabled
    in this case.
  4. defer creation of reset request lines to the realize function, as the number of reset active lines are not know before this execution point.
  5. ensure all traces emit the ot_id string

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(splitted single commit into commits with distinct features)

@rivos-eblot rivos-eblot marked this pull request as ready for review October 17, 2025 08:01
Also split up ot_aon_timer_get_wdog_count

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Fix constant definitions and bitfields that were still hardcoded for a specific
top (likely EarlGrey)

Replace some constants with top-dependent macros

Defer creation of reset request lines to the realize function, as the number
of reset active lines are not know before this execution point.

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
…ain crossing

Several register properties are not used as-is, as they drive features implemented in
the slow clock domain, while the registers themselves are in the default, "fast" clock
domain.

It is required for the guest SW to write and poll the CFG_CDC_SYNC register to
commit new settings to the slow clock domain.

QEMU was not supporting this feature, the guest SW could then miss to synchronize
these features. Application would have run fine on QEMU but not on the real HW.

Note that the doc is out-of-date, and only the RTL can provide a list of the actual
slow clock domain features gated by the CFG_CDC_DOMAIN.

Also update the guest error message to give a hint when reset cannot be successfully
enabled in this case.

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
@rivos-eblot rivos-eblot force-pushed the dev/ebl/pwrmgr_upgrade branch from e9ed953 to 53e44bf Compare October 17, 2025 10:44
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LGTM, thanks.

Note that the doc is out-of-date, and only the RTL can provide a list of the actual
slow clock domain features gated by the CFG_CDC_DOMAIN.

Is this an OT doc deficiency? Do you know if it is documented in an issue upstream anywhere?

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rivos-eblot commented Oct 17, 2025

Is this an OT doc deficiency?

May be not a true deficiency, but rather a lack of details.
In PwrMgr doc CFG_CDC_DOMAIN is described for Entering Low Power and Exiting Low Power, but not for allowing HW reset. It could be deducted from the registers that are modified (RESET_EN) ... maybe.

To be honest, I stopped tracking all the discrepencies between the OT doc and the actual RTL, there are far too many and often very subtle, such as this one, so ... documenting them through tickets take too much time unfortunately. I wrote a couple of them. BTW if the CSS issues could be addressed, that would be very nice, as tweaking the CSS in the browser to get access to the content is not very convenient.

I think the real issue is that CFG_CDC_DOMAIN usage should be referenced in the documentation for RESET_EN at least, so it is made clear that one depends on the other.

Do you know if it is documented in an issue upstream anywhere?

Sorry, I have not checked.

@rivos-eblot rivos-eblot merged commit eb1610d into lowRISC:ot-9.2.0 Oct 17, 2025
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@rivos-eblot rivos-eblot deleted the dev/ebl/pwrmgr_upgrade branch October 17, 2025 12:09
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2 participants