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ot_soc_dbg_ctrl: rewrite SoC debug controller implementation #278

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Merged
merged 24 commits into from
Nov 12, 2025
Merged

ot_soc_dbg_ctrl: rewrite SoC debug controller implementation #278

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a722da1
[ot] hw/opentitan: ot_lc_ctrl: add RMA broadcast signal
rivos-eblot Nov 4, 2025
58465eb
[ot] hw/opentitan: ot_lc_ctrl: rename SOCDBG as SOC_DBG to match new HW
rivos-eblot Nov 7, 2025
37e44a6
[ot] hw/opentitan: ot_lc_ctrl: rename soc_dbg property
rivos-eblot Nov 7, 2025
4d21a40
[ot] hw/opentitan: ot_lc_ctrl: add new API to retrieve soc debug stat…
rivos-eblot Nov 7, 2025
d36f37f
[ot] hw/opentitan: ot_pwrmgr: rename `irq` in ROM handlers
rivos-eblot Nov 7, 2025
c92365d
[ot] hw/opentitan: ot_pwrmgr: rename boot status signals to match new HW
rivos-eblot Nov 7, 2025
a13fe86
[ot] hw/opentitan: ot_pwrmgr: use ROM constants for bitfield widths
rivos-eblot Nov 7, 2025
14e55cd
[ot] hw/opentitan: ot_common: add multibit bool bitmask and width def…
rivos-eblot Nov 7, 2025
9b79401
[ot] hw/opentitan: ot_soc_dbg_ctrl: rename files
rivos-eblot Nov 7, 2025
addf916
[ot] hw/opentitan: ot_soc_dbg_ctrl: rename variable and constants
rivos-eblot Nov 7, 2025
37986e4
[ot] hw/opentitan: ot_soc_dbg_ctrl: rename deprecated signals
rivos-eblot Nov 7, 2025
26b1908
[ot] hw/opentitan: ot_soc_dbg_ctrl: rename `RAW` SoC debug state as `…
rivos-eblot Nov 7, 2025
af35a49
[ot] hw/opentitan: ot_soc_dbg_ctrl: remove lock/unlock properties
rivos-eblot Nov 7, 2025
25eeb6a
[ot] hw/opentitan: ot_soc_dbg_ctrl: rename DMI as JTAG
rivos-eblot Nov 7, 2025
65038da
[ot] hw/opentitan: ot_soc_dbg_ctrl: rename `cpu_boot` as `continue_cp…
rivos-eblot Nov 7, 2025
daf37df
[ot] hw/opentitan: ot_soc_dbg_ctrl: remove IRQ managemnt
rivos-eblot Nov 7, 2025
c37d3de
[ot] hw/opentitan: ot_soc_dbg_ctrl: update ALERT management
rivos-eblot Nov 7, 2025
6a8da39
[ot] hw/opentitan: ot_soc_dbg_ctrl: redefine state machine and signal…
rivos-eblot Nov 12, 2025
dcf2c0b
[ot] hw/opentitan: ot_soc_dbg_ctrl: retrieve SoC debug code from LC c…
rivos-eblot Nov 12, 2025
090d4a5
[ot] hw/opentitan: ot_soc_dbg_ctrl: decode debug policy and update ou…
rivos-eblot Nov 12, 2025
75b206b
[ot] hw/riscv: ot_darjeeling: update Soc Debug controller configuration
rivos-eblot Nov 7, 2025
5f8ce57
[ot] python/qemu: ot.lc_ctrl: rename 'socdbg' as 'soc_dbg'
rivos-eblot Nov 7, 2025
bcc42aa
[ot] scripts/opentitan: darjeeling.cfg: update OpenOCD script
rivos-eblot Nov 7, 2025
f32a873
[ot] docs/config: opentitan: update Darjeeling configuration
rivos-eblot Nov 7, 2025
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8 changes: 4 additions & 4 deletions docs/config/opentitan/darjeeling.cfg
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Original file line number Diff line number Diff line change
@@ -1,5 +1,4 @@
# Generated from OpenTitan 'master' branch
# commit: fc2d73b432
# Generated from OpenTitan commit: c5507b4cdc

[ot_device "ot-rom_ctrl.rom0"]
key = "30ae84156d37cc68063276f9e85faee1"
Expand Down Expand Up @@ -39,8 +38,8 @@
production = "ffc2171a49199bb53d8e0daa8f0578db"
raw_unlock_token = "e4225dc332ea1fda63b4c524556ed4d4"
rma = "aa5f022791480b4e709e0f80976e0966"
socdbg_first = "6b36fc2c"
socdbg_last = "ebf6fc7f"
soc_dbg_first = "6b36fc2c"
soc_dbg_last = "ebf6fc7f"
test_unlocked = "e4c72c47d9e15fa8ff9f82833e32c151"

[ot_device "ot-keymgr_dpe"]
Expand All @@ -67,3 +66,4 @@

[ot_device "ot-pwrmgr"]
clocks = "main,io"

2 changes: 1 addition & 1 deletion docs/opentitan/ot_darjeeling.md
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ Please check out `hw/opentitan/ot_ref.log`
* zero-ization is not yet supported
* [RISC-V Debug Module](jtag-dm.md) and Pulp Debug Module
* [ROM controller](ot_rom_ctrl.md)
* [SoC debug controller documentation](ot_socdbg_ctrl.md)
* [SoC debug controller documentation](ot_soc_dbg_ctrl.md)
* SPI data flash (from QEMU upstream w/ fixes)
* [SPI Host controller](ot_spi_host.md)
* HW bus config is ignored (SPI mode, speed, ...)
Expand Down
0 docs/opentitan/ot_socdbg_ctrl.md → docs/opentitan/ot_soc_dbg_ctrl.md
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2 changes: 1 addition & 1 deletion hw/opentitan/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -191,7 +191,7 @@ config OT_SENSOR_EG
config OT_SOC_PROXY
bool

config OT_SOCDBG_CTRL
config OT_SOC_DBG_CTRL
bool

config OT_SPI_DEVICE
Expand Down
2 changes: 1 addition & 1 deletion hw/opentitan/meson.build
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Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,7 @@ system_ss.add(when: 'CONFIG_OT_ROM_CTRL', if_true: files('ot_rom_ctrl.c', 'ot_ro
system_ss.add(when: 'CONFIG_OT_RSTMGR', if_true: files('ot_rstmgr.c'))
system_ss.add(when: 'CONFIG_OT_SENSOR_EG', if_true: files('ot_sensor_eg.c'))
system_ss.add(when: 'CONFIG_OT_SOC_PROXY', if_true: files('ot_soc_proxy.c'))
system_ss.add(when: 'CONFIG_OT_SOCDBG_CTRL', if_true: files('ot_socdbg_ctrl.c'))
system_ss.add(when: 'CONFIG_OT_SOC_DBG_CTRL', if_true: files('ot_soc_dbg_ctrl.c'))
system_ss.add(when: 'CONFIG_OT_SPI_DEVICE', if_true: files('ot_spi_device.c'))
system_ss.add(when: 'CONFIG_OT_SPI_HOST', if_true: files('ot_spi_host.c'))
system_ss.add(when: 'CONFIG_OT_SRAM_CTRL', if_true: files('ot_sram_ctrl.c'))
Expand Down
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