Encoder work adc fix #101
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Encoder work adc fix #101
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…pare Signed-off-by: Michael Brown <producer@holotronic.dk>
…with cap sensor Signed-off-by: Michael Brown <producer@holotronic.dk>
…sion) Signed-off-by: Michael Brown <producer@holotronic.dk>
…nd update firmware id Signed-off-by: Michael Brown <producer@holotronic.dk>
Signed-off-by: Michael Brown <producer@holotronic.dk>
… restore former Signed-off-by: Michael Brown <producer@holotronic.dk>
… read upto 24 bits in the hal) Cosmetic changes: change all line ends to msdos type as this is what quartus produces Change all tabs to soft tabs (4 spaces) Rename ADC data input signal to: measured_data Signed-off-by: Michael Brown <producer@holotronic.dk>
Cosmetic changes: change all line ends to msdos type as this is what quartus produces Change all tabs to soft tabs (4 spaces) Signed-off-by: Michael Brown <producer@holotronic.dk>
Due to a bug in qsys the ADC clock was running at 50Mhz making it's behaviour inconsistant as it is rated for max 40Mhz. Fixed by moving the clock signal source to a qsys pll keeping qsys soc system pinouts unaltered. Signed-off-by: Michael Brown <producer@holotronic.dk>
ArcEye
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May 8, 2019
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I'll defer to @cdsteinkuehler on this.
What little knowledge I have in this area is restricted to massaging the package build back to life
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This PR Concerns only the DE10_Nano_FB_Cramps and DE0_Nano_Soc_Cramps designs:
Adds: Routing input pins to Mesa VHDL cores
Adds: config with 2x (qcounter) encoder inputs on GPIO_1
Fixes ADC reading (Qsys HPS clock generated a 50MHz adc clock instead of the specified 40Mhz)
ADC and Encoder functionality tested OK