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Merged
merged 9 commits into from
May 8, 2019
Merged

Encoder work adc fix #101

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26d422a
DExx Cramps: whitespace cleanup in top files, making it easier to com…
the-snowwhite Apr 26, 2019
4d4ddcc
DE_10xx_Cramps: change default quartus compilable project to version …
the-snowwhite May 2, 2019
c6b7c18
DE_0xx_Cramps: add default quartus compilable project (cap sensor ver…
the-snowwhite May 2, 2019
bd11c5a
DE10xxxCramps: fix copy paste error, update to 2 encoders with pins …
the-snowwhite May 2, 2019
978761a
DExx..xxCramps: Route input pins to Hostmot core and update id
the-snowwhite May 2, 2019
ddde23e
DExx_Cramps: move now tested encoder config into new config files and…
the-snowwhite May 3, 2019
c796211
ADC: Moce channel number to MSB in Data samples (makes it possible to…
the-snowwhite May 7, 2019
0fd4729
Remove bus buffers from adc core, to improve access timing.
the-snowwhite May 7, 2019
ded1496
DE10_Nano_FB_Cramps + DE0_Nano_SoC: ADC fix
the-snowwhite May 7, 2019
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213 changes: 105 additions & 108 deletions HW/QuartusProjects/Common/adc_ltc2308.v
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Original file line number Diff line number Diff line change
@@ -1,132 +1,132 @@
module adc_ltc2308(
clk, // max 40mhz
// start measure
measure_start, // posedge triggle
measure_ch,
measure_done,
measure_dataread,
// adc interface
ADC_CONVST,
ADC_SCK,
ADC_SDI,
ADC_SDO
clk, // max 40mhz

// start measure
measure_start, // posedge triggle
measure_ch,
measure_done,
measured_data,

// adc interface
ADC_CONVST,
ADC_SCK,
ADC_SDI,
ADC_SDO
);

input clk;
input clk;

// start measure
input measure_start;
input [2:0] measure_ch;
output reg measure_done;
output [11:0] measure_dataread;
input measure_start;
input [2:0] measure_ch;
output reg measure_done;
output reg [11:0] measured_data;



output ADC_CONVST;
output ADC_SCK;
output reg ADC_SDI;
input ADC_SDO;
output ADC_CONVST;
output ADC_SCK;
output reg ADC_SDI;
input ADC_SDO;


/////////////////////////////////
// Timing definition
// Timing definition

// using 40MHz clock
// to acheive fsample = 500KHz
// ntcyc = 2us / 25ns = 80



`define DATA_BITS_NUM 12
`define CMD_BITS_NUM 6
`define CH_NUM 8
`define DATA_BITS_NUM 12
`define CMD_BITS_NUM 6
`define CH_NUM 8

`define tWHCONV 1 // CONVST High Time, min 20 ns
`define tCONV 64 //52 // tCONV: type 1.3 us, MAX 1.6 us, 1600/25(assumed clk is 40mhz)=64 -> 1.3us/25ns = 52
// set 64 for suite for 1.6 us max
// +12 //data
`define tWHCONV 1 // CONVST High Time, min 20 ns
`define tCONV 64 //52 // tCONV: type 1.3 us, MAX 1.6 us, 1600/25(assumed clk is 40mhz)=64 -> 1.3us/25ns = 52
// set 64 for suite for 1.6 us max
// +12 //data

`define tHCONVST 320 // 12 // here set 320（ fsample = 100KHz） for if ADC input impedance is high, see below
`define tHCONVST 320 // 12 // here set 320（ fsample = 100KHz） for if ADC input impedance is high, see below
// If the source impedance of the driving circuit is low, the ADC inputs can be driven directly.
//Otherwise, more acquisition time should be allowed for a source with higher impedance.

// for acheiving 500KHz fmax. set n cyc = 80.
`define tCONVST_HIGH_START 0
`define tCONVST_HIGH_END (`tCONVST_HIGH_START+`tWHCONV)
// for acheiving 500KHz fmax. set n cyc = 80.
`define tCONVST_HIGH_START 0
`define tCONVST_HIGH_END (`tCONVST_HIGH_START+`tWHCONV)

`define tCONFIG_START (`tCONVST_HIGH_END)
`define tCONFIG_END (`tCLK_START+`CMD_BITS_NUM - 1)
`define tCONFIG_START (`tCONVST_HIGH_END)
`define tCONFIG_END (`tCLK_START+`CMD_BITS_NUM - 1)

`define tCLK_START (`tCONVST_HIGH_START+`tCONV)
`define tCLK_END (`tCLK_START+`DATA_BITS_NUM)
`define tCLK_START (`tCONVST_HIGH_START+`tCONV)
`define tCLK_END (`tCLK_START+`DATA_BITS_NUM)

`define tDONE (`tCLK_END+`tHCONVST)
`define tDONE (`tCLK_END+`tHCONVST)

// create triggle message: reset_n
reg pre_measure_start;
always @ (posedge clk)
always @ (posedge clk)
begin
pre_measure_start <= measure_start;
pre_measure_start <= measure_start;
end

wire reset_n;
assign reset_n = (!pre_measure_start & measure_start)?1'b0:1'b1;

// tick
reg [15:0] tick;
always @ (posedge clk or negedge reset_n)
reg [15:0] tick;
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
tick <= 0;
else if (tick < `tDONE)
tick <= tick + 1;
if (!reset_n)
tick <= 0;
else if (tick < `tDONE)
tick <= tick + 1;
end


/////////////////////////////////
// ADC_CONVST
// ADC_CONVST
assign ADC_CONVST = (tick >= `tCONVST_HIGH_START && tick < `tCONVST_HIGH_END)?1'b1:1'b0;

/////////////////////////////////
// ADC_SCK
// ADC_SCK

reg clk_enable; // must sync to clk in clk low
always @ (negedge clk or negedge reset_n)
always @ (negedge clk or negedge reset_n)
begin
if (!reset_n)
clk_enable <= 1'b0;
else if ((tick >= `tCLK_START && tick < `tCLK_END))
clk_enable <= 1'b1;
else
clk_enable <= 1'b0;
if (!reset_n)
clk_enable <= 1'b0;
else if ((tick >= `tCLK_START && tick < `tCLK_END))
clk_enable <= 1'b1;
else
clk_enable <= 1'b0;
end

assign ADC_SCK = clk_enable?clk:1'b0;


///////////////////////////////
// read data
reg [(`DATA_BITS_NUM-1):0] read_data;
//reg [(`DATA_BITS_NUM-1):0] measured_data;
reg [3:0] write_pos;



assign measure_dataread = read_data;
assign measured_data = measured_data;

always @ (negedge clk or negedge reset_n)
always @ (negedge clk or negedge reset_n)
begin
if (!reset_n)
begin
read_data <= 0;
write_pos <= `DATA_BITS_NUM-1;
end
else if (clk_enable)
begin
read_data[write_pos] <= ADC_SDO;
write_pos <= write_pos - 1;
end
if (!reset_n)
begin
measured_data <= 0;
write_pos <= `DATA_BITS_NUM-1;
end
else if (clk_enable)
begin
measured_data[write_pos] <= ADC_SDO;
write_pos <= write_pos - 1;
end
end

///////////////////////////////
Expand All @@ -135,12 +135,12 @@ wire read_ch_done;

assign read_ch_done = (tick == `tDONE)?1'b1:1'b0;

always @ (posedge clk or negedge reset_n)
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
measure_done <= 1'b0;
else if (read_ch_done)
measure_done <= 1'b1;
if (!reset_n)
measure_done <= 1'b0;
else if (read_ch_done)
measure_done <= 1'b1;
end

///////////////////////////////
Expand All @@ -150,25 +150,25 @@ end
reg [(`CMD_BITS_NUM-1):0] config_cmd;


`define UNI_MODE 1'b1 //1: Unipolar, 0:Bipolar
`define SLP_MODE 1'b0 //1: enable sleep
`define UNI_MODE 1'b1 //1: Unipolar, 0:Bipolar
`define SLP_MODE 1'b0 //1: enable sleep

always @(negedge reset_n)
begin
if (!reset_n)
begin
case (measure_ch)
0 : config_cmd <= {4'h8, `UNI_MODE, `SLP_MODE};
1 : config_cmd <= {4'hC, `UNI_MODE, `SLP_MODE};
2 : config_cmd <= {4'h9, `UNI_MODE, `SLP_MODE};
3 : config_cmd <= {4'hD, `UNI_MODE, `SLP_MODE};
4 : config_cmd <= {4'hA, `UNI_MODE, `SLP_MODE};
5 : config_cmd <= {4'hE, `UNI_MODE, `SLP_MODE};
6 : config_cmd <= {4'hB, `UNI_MODE, `SLP_MODE};
7 : config_cmd <= {4'hF, `UNI_MODE, `SLP_MODE};
default : config_cmd <= {4'hF, 2'b00};
endcase
end
if (!reset_n)
begin
case (measure_ch)
0 : config_cmd <= {4'h8, `UNI_MODE, `SLP_MODE};
1 : config_cmd <= {4'hC, `UNI_MODE, `SLP_MODE};
2 : config_cmd <= {4'h9, `UNI_MODE, `SLP_MODE};
3 : config_cmd <= {4'hD, `UNI_MODE, `SLP_MODE};
4 : config_cmd <= {4'hA, `UNI_MODE, `SLP_MODE};
5 : config_cmd <= {4'hE, `UNI_MODE, `SLP_MODE};
6 : config_cmd <= {4'hB, `UNI_MODE, `SLP_MODE};
7 : config_cmd <= {4'hF, `UNI_MODE, `SLP_MODE};
default : config_cmd <= {4'hF, 2'b00};
endcase
end
end

// serial config command to adc chip
Expand All @@ -177,27 +177,24 @@ wire config_enable;
wire config_done;
reg [2:0] sdi_index;

assign config_init = (tick == `tCONFIG_START)?1'b1:1'b0;
assign config_init = (tick == `tCONFIG_START)?1'b1:1'b0;
assign config_enable = (tick > `tCLK_START && tick <= `tCONFIG_END)?1'b1:1'b0; // > because this is negative edge triggle
assign config_done = (tick > `tCONFIG_END)?1'b1:1'b0;
always @(negedge clk)
assign config_done = (tick > `tCONFIG_END)?1'b1:1'b0;
always @(negedge clk)
begin
if (config_init)
begin
ADC_SDI <= config_cmd[`CMD_BITS_NUM-1];
sdi_index <= `CMD_BITS_NUM-2;
end
else if (config_enable)
begin
ADC_SDI <= config_cmd[sdi_index];
sdi_index <= sdi_index - 1;
end
else if (config_done)
ADC_SDI <= 1'b0; //
if (config_init)
begin
ADC_SDI <= config_cmd[`CMD_BITS_NUM-1];
sdi_index <= `CMD_BITS_NUM-2;
end
else if (config_enable)
begin
ADC_SDI <= config_cmd[sdi_index];
sdi_index <= sdi_index - 1;
end
else if (config_done)
ADC_SDI <= 1'b0; //
end




endmodule

9 changes: 4 additions & 5 deletions HW/QuartusProjects/Common/adc_ltc2308_fifo.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -74,10 +74,9 @@ begin
if (slave_read_status)
readdataout <= {4'b0, measure_fifo_num, 9'b0, measure_fifo_ch, 3'b0, measure_fifo_done};
else if (slave_read_data)
readdataout <= {13'b0, fifo_ch_q, 4'b0, fifo_q};
readdataout <= {1'b0, fifo_ch_q, 16'b0, fifo_q};
end

//reg [1:0] post_read_outdata;
reg post_read_outdata;
reg fifo_rdreq;
always @ (posedge clock or negedge reset_n)
Expand Down Expand Up @@ -118,7 +117,7 @@ reg config_first;
reg wait_measure_done;
reg measure_start;
wire measure_done;
wire [11:0] measure_dataread;
wire [11:0] measured_data;

// auto channel change
//wire [2:0] adc_ch_sel = (auto_ch_select) ? 3'h7:measure_fifo_ch;
Expand Down Expand Up @@ -200,7 +199,7 @@ adc_ltc2308 adc_ltc2308_inst(
.measure_start(measure_start), // posedge triggle
.measure_done(measure_done),
.measure_ch(adc_ch),
.measure_dataread(measure_dataread),
.measured_data(measured_data),


// adc interface
Expand All @@ -215,7 +214,7 @@ adc_ltc2308 adc_ltc2308_inst(

adc_data_fifo adc_data_fifo_inst(
.aclr(adc_reset),
.data({adc_ch_dly, measure_dataread}),
.data({adc_ch_dly, measured_data}),
// .rdclk(read_outdata),
.rdclk(clock),
.rdreq(fifo_rdreq),
Expand Down
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