Skip to content

Update addresses of qsys cores to be consistent across quartus projects #98

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 5 commits into from
Jun 8, 2018
Merged

Update addresses of qsys cores to be consistent across quartus projects #98

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
5 commits
Select commit Hold shift + click to select a range
1a812a8
Updated addresses of qsys cores to be consistant,
the-snowwhite May 30, 2018
30720d7
Correct qsys external signals
the-snowwhite May 30, 2018
40f00ab
move interrupt capturer to 0x0000_0f00
the-snowwhite Jun 1, 2018
3db8287
Rename display clock signal
the-snowwhite Jun 5, 2018
c6ef9cf
Add readme
the-snowwhite Jun 5, 2018
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
173 changes: 130 additions & 43 deletions HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system.qsys
View file
Open in desktop

Large diffs are not rendered by default.

9 changes: 1 addition & 8 deletions HW/QuartusProjects/DE0_Nano_SoC_DB25/DE0_Nano_SoC_DB25.vhd
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -275,14 +275,7 @@ begin
-- mk_io_hm2_we => hm_chipsel, -- .hm2_chipsel
mk_io_hm2_int_in => irq, -- .hm2_int_in
clk_100mhz_out_clk => hm_clk_med, -- clk_100mhz_out.clk
clk_200mhz_out_clk => hm_clk_high, -- clk_100mhz_out.clk
adc_io_convst => ADC_CONVST, -- adc.CONVST
adc_io_sck => ADC_SCK, -- .SCK
adc_io_sdi => ADC_SDI, -- .SDI
adc_io_sdo => ADC_SDO -- .SDO
-- axi_str_data => out_data[7:0], -- stream_port.data
-- axi_str_valid => out_data[8], -- .valid
-- axi_str_ready => ar_in_sig[1]) -- .ready
clk_200mhz_out_clk => hm_clk_high -- clk_100mhz_out.clk
);

-- Debounce logic to clean out glitches within 1ms
Expand Down
Loading